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author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-03-26 15:14:04 +0000 |
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committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-03-26 15:14:04 +0000 |
commit | afaeb8152c79a9f3c157a614331d6919a0a0fa6a (patch) | |
tree | 5962a3a26693d4d02744b16c9e809094b6234d56 /lib/Target/ARM/ARMScheduleSwift.td | |
parent | d6f5a581ab968a2618b0c5a8472ea2ab37797916 (diff) |
Revert ARM Scheduler Model: Add resources instructions, map resources
This reverts commit r177968. It is causing failures in a local build bot.
"fatal error: error in backend: Expected a variant SchedClass"
Original commit message:
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178028 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleSwift.td')
-rw-r--r-- | lib/Target/ARM/ARMScheduleSwift.td | 23 |
1 files changed, 1 insertions, 22 deletions
diff --git a/lib/Target/ARM/ARMScheduleSwift.td b/lib/Target/ARM/ARMScheduleSwift.td index becf41b0efe..e9bc3e0f395 100644 --- a/lib/Target/ARM/ARMScheduleSwift.td +++ b/lib/Target/ARM/ARMScheduleSwift.td @@ -1078,29 +1078,8 @@ def SwiftModel : SchedMachineModel { let IssueWidth = 3; // 3 micro-ops are dispatched per cycle. let MinLatency = 0; // Data dependencies are allowed within dispatch groups. let LoadLatency = 3; - let MispredictPenalty = 14; // A branch direction mispredict. let Itineraries = SwiftItineraries; } -// Swift resource mapping. -let SchedModel = SwiftModel in { - // Processor resources. - def SwiftUnitP01 : ProcResource<2>; // ALU unit. - def SwiftUnitP0 : ProcResource<1> { let Super = SwiftUnitP01; } // Mul unit. - def SwiftUnitP1 : ProcResource<1> { let Super = SwiftUnitP01; } // Br unit. - def SwiftUnitP2 : ProcResource<1>; // LS unit. - def SwiftUnitDiv : ProcResource<1>; - - // 4.2.4 Arithmetic and Logical. - // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR - // AND,BIC, EOR,ORN,ORR - // CLZ,RBIT,REV,REV16,REVSH,PKH - // Single cycle. - def : WriteRes<WriteALU, [SwiftUnitP01]>; - def : WriteRes<WriteALUsi, [SwiftUnitP01]>; - def : WriteRes<WriteALUsr, [SwiftUnitP01]>; - def : WriteRes<WriteALUSsr, [SwiftUnitP01]>; - def : ReadAdvance<ReadAdvanceALU, 0>; - def : ReadAdvance<ReadAdvanceALUsr, 2>; -} +// TODO: Add Swift processor and scheduler resources. |