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| author | tstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8> | 2012-09-25 13:59:15 +0000 |
|---|---|---|
| committer | tstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8> | 2012-09-25 13:59:15 +0000 |
| commit | aa462ea5e0b841b6bfaf7646132df78df750cb74 (patch) | |
| tree | 067030b847d3f213f31005b1fe01c648f145a54a /lib/Target/AMDGPU | |
| parent | 18e0b9e13783459ef7ad04180cc099315122fbc1 (diff) | |
R600: Fix typo in R600RegisterInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164603 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AMDGPU')
| -rw-r--r-- | lib/Target/AMDGPU/R600RegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/AMDGPU/R600RegisterInfo.td b/lib/Target/AMDGPU/R600RegisterInfo.td index 21269535bc2..b6b8eea16da 100644 --- a/lib/Target/AMDGPU/R600RegisterInfo.td +++ b/lib/Target/AMDGPU/R600RegisterInfo.td @@ -49,7 +49,7 @@ def R600_CReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (interleave (sequence "C%u_X", 0, 127), (sequence "C%u_Z", 0, 127)), (interleave (sequence "C%u_Y", 0, 127), - (sequence "C%u_Z", 0, 127))))>; + (sequence "C%u_W", 0, 127))))>; def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32, (add (sequence "T%u_X", 0, 127))>; |