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authortstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-10-15 20:53:37 +0000
committertstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-10-15 20:53:37 +0000
commita5758180dfc5d2000739c9296111ad93ad79b657 (patch)
treea2575fddc1119bbaca600b4345043511b9a435f2 /lib/Target/AMDGPU/R600RegisterInfo.td
parent02761281c3fac90e8e8e2ef63cbee64beb61614b (diff)
R600: Store channel index in the register's HWEncoding field
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165965 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AMDGPU/R600RegisterInfo.td')
-rw-r--r--lib/Target/AMDGPU/R600RegisterInfo.td16
1 files changed, 14 insertions, 2 deletions
diff --git a/lib/Target/AMDGPU/R600RegisterInfo.td b/lib/Target/AMDGPU/R600RegisterInfo.td
index b6b8eea16da..58c6c3564cf 100644
--- a/lib/Target/AMDGPU/R600RegisterInfo.td
+++ b/lib/Target/AMDGPU/R600RegisterInfo.td
@@ -4,6 +4,18 @@ class R600Reg <string name, bits<16> encoding> : Register<name> {
let HWEncoding = encoding;
}
+class R600RegWithChan <string name, bits<9> sel, string chan> :
+ Register <name> {
+
+ field bits<2> chan_encoding = !if(!eq(chan, "X"), 0,
+ !if(!eq(chan, "Y"), 1,
+ !if(!eq(chan, "Z"), 2,
+ !if(!eq(chan, "W"), 3, 0))));
+ let HWEncoding{8-0} = sel;
+ let HWEncoding{10-9} = chan_encoding;
+ let Namespace = "AMDGPU";
+}
+
class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
RegisterWithSubRegs<n, subregs> {
let Namespace = "AMDGPU";
@@ -14,11 +26,11 @@ class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
foreach Index = 0-127 in {
foreach Chan = [ "X", "Y", "Z", "W" ] in {
// 32-bit Temporary Registers
- def T#Index#_#Chan : R600Reg <"T"#Index#"."#Chan, Index>;
+ def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>;
// 32-bit Constant Registers (There are more than 128, this the number
// that is currently supported.
- def C#Index#_#Chan : R600Reg <"C"#Index#"."#Chan, Index>;
+ def C#Index#_#Chan : R600RegWithChan <"C"#Index#"."#Chan, Index, Chan>;
}
// 128-bit Temporary Registers
def T#Index#_XYZW : R600Reg_128 <"T"#Index#".XYZW",