diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2012-10-08 15:37:39 +0200 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2012-10-17 19:20:27 +0000 |
| commit | 831c5c82f3fc1899e51d1bd976587f4c2b4ef84f (patch) | |
| tree | a511a6903b658af6636aafc5eed9eab58b470ec5 /lib/Target/AMDGPU/R600RegisterInfo.td | |
| parent | fbadea4f5104ea7da8eedf7d134ec513ba94f4e9 (diff) | |
R600: Use native operands for R600_1OP instructions
Diffstat (limited to 'lib/Target/AMDGPU/R600RegisterInfo.td')
| -rw-r--r-- | lib/Target/AMDGPU/R600RegisterInfo.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/AMDGPU/R600RegisterInfo.td b/lib/Target/AMDGPU/R600RegisterInfo.td index 58c6c3564cf..c682f2bf09f 100644 --- a/lib/Target/AMDGPU/R600RegisterInfo.td +++ b/lib/Target/AMDGPU/R600RegisterInfo.td @@ -53,8 +53,8 @@ def ALU_LITERAL_X : R600Reg<"literal.x", 253>; def PV_X : R600Reg<"pv.x", 254>; def PREDICATE_BIT : R600Reg<"PredicateBit", 0>; def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>; -def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 0>; -def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 0>; +def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>; +def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>; def R600_CReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add (interleave |