summaryrefslogtreecommitdiff
path: root/lib/Target/AMDGPU/R600RegisterInfo.td
diff options
context:
space:
mode:
authortstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-09-25 13:59:13 +0000
committertstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-09-25 13:59:13 +0000
commit18e0b9e13783459ef7ad04180cc099315122fbc1 (patch)
treec5f7a47cd1ba984c19583c5b0ca90555e3050daf /lib/Target/AMDGPU/R600RegisterInfo.td
parent702e6564a2eb45a6cf8dd2ed9e58cbc57ebd3a17 (diff)
AMDGPU: Fix register encoding
The register encodings weren't being defined correctly in the .td files, so they were all encoded as 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164602 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AMDGPU/R600RegisterInfo.td')
-rw-r--r--lib/Target/AMDGPU/R600RegisterInfo.td6
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/AMDGPU/R600RegisterInfo.td b/lib/Target/AMDGPU/R600RegisterInfo.td
index 37345c603e2..21269535bc2 100644
--- a/lib/Target/AMDGPU/R600RegisterInfo.td
+++ b/lib/Target/AMDGPU/R600RegisterInfo.td
@@ -14,11 +14,11 @@ class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
foreach Index = 0-127 in {
foreach Chan = [ "X", "Y", "Z", "W" ] in {
// 32-bit Temporary Registers
- def T#Index#_#Chan : R600Reg <"T"#Index#"."#Chan, !cast<bits<16>>(Index)>;
+ def T#Index#_#Chan : R600Reg <"T"#Index#"."#Chan, Index>;
// 32-bit Constant Registers (There are more than 128, this the number
// that is currently supported.
- def C#Index#_#Chan : R600Reg <"C"#Index#"."#Chan, !cast<bits<16>>(Index)>;
+ def C#Index#_#Chan : R600Reg <"C"#Index#"."#Chan, Index>;
}
// 128-bit Temporary Registers
def T#Index#_XYZW : R600Reg_128 <"T"#Index#".XYZW",
@@ -26,7 +26,7 @@ foreach Index = 0-127 in {
!cast<Register>("T"#Index#"_Y"),
!cast<Register>("T"#Index#"_Z"),
!cast<Register>("T"#Index#"_W")],
- !cast<bits<16>>(Index)>;
+ Index>;
}
// Special Registers