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| author | Tom Stellard <thomas.stellard@amd.com> | 2012-10-12 21:40:51 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2012-10-12 21:40:51 +0000 |
| commit | 9636fec7d8c4f8ca55341544c1eecbf39d6b0db2 (patch) | |
| tree | b2eb2373b796eedf00e84225a0ef130c1407aefe /lib/Target/AMDGPU/R600Defines.h | |
| parent | 8582a17947bd0f1f392a5954ba49bb98539fea97 (diff) | |
XXX: WIP no MIOperandInfo waybackup-Oct15
Diffstat (limited to 'lib/Target/AMDGPU/R600Defines.h')
| -rw-r--r-- | lib/Target/AMDGPU/R600Defines.h | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/lib/Target/AMDGPU/R600Defines.h b/lib/Target/AMDGPU/R600Defines.h index 8191c6a64a7..962f4888c5f 100644 --- a/lib/Target/AMDGPU/R600Defines.h +++ b/lib/Target/AMDGPU/R600Defines.h @@ -33,8 +33,9 @@ namespace R600_InstFlag { FC = (1 << 3), TRIG = (1 << 4), OP3 = (1 << 5), - VECTOR = (1 << 6) + VECTOR = (1 << 6), //FlagOperand bits 7, 8 + HAS_NATIVE_OPERANDS = (1 << 9) }; } @@ -42,4 +43,20 @@ namespace R600_InstFlag { #define HW_REG_MASK 0x1ff #define HW_CHAN_SHIFT 9 +namespace R600Op2OperandIndex { + enum ROI { + SRC0, + SRC0_NEG, + SRC0_REL, + IMM0, + SRC1, + SRC1_REL, + SRC1_NEG, + IMM1, + INDEX_MODE, + PRED_SEL, + LAST + }; +} + #endif // R600DEFINES_H_ |