diff options
| author | tstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8> | 2012-09-25 13:59:13 +0000 |
|---|---|---|
| committer | tstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8> | 2012-09-25 13:59:13 +0000 |
| commit | 18e0b9e13783459ef7ad04180cc099315122fbc1 (patch) | |
| tree | c5f7a47cd1ba984c19583c5b0ca90555e3050daf /lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp | |
| parent | 702e6564a2eb45a6cf8dd2ed9e58cbc57ebd3a17 (diff) | |
AMDGPU: Fix register encoding
The register encodings weren't being defined correctly in the .td files,
so they were all encoded as 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164602 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp index 8dfb095d548..274400aa34a 100644 --- a/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp @@ -623,13 +623,7 @@ unsigned R600MCCodeEmitter::getHWRegChan(unsigned reg) const { } } unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const { - unsigned HWReg; - - HWReg = MRI.getEncodingValue(RegNo); - if (AMDGPUMCRegisterClasses[AMDGPU::R600_CReg32RegClassID].contains(RegNo)) { - HWReg += 512; - } - return HWReg; + return MRI.getEncodingValue(RegNo); } uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, |