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authorTom Stellard <thomas.stellard@amd.com>2015-10-15 15:44:04 +0000
committerTom Stellard <thomas.stellard@amd.com>2015-10-15 15:44:04 +0000
commitc5ca856fc459a5cc9b6d66fec98c969e70e9d2fb (patch)
tree275f8483fde01fee96767de8e98483ee00564d95
parent055af7d7ea079a3f9ee8f5639f4f22c84d3cd5f9 (diff)
XXX: Rebase fix
-rw-r--r--lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp17
1 files changed, 0 insertions, 17 deletions
diff --git a/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 09cc9a6fa34..73b87b082e2 100644
--- a/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -560,23 +560,6 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
case AMDGPUISD::DIV_SCALE: {
return SelectDIV_SCALE(N);
}
- case AMDGPUISD::BRCOND_UNIFORM: {
- SDValue Cond = N->getOperand(0);
-
- // Let TableGen handle this case:
-// if (!Cond.getOpcode() == ISD::SETCC)
-// break;
-
- const SDValue Ops[] = {
- N->getOperand(1),
- N->getOperand(2)
- };
-
- return CurDAG->getMachineNode(AMDGPU::S_CBRANCH_SCC1, SDLoc(N),
- MVT::Other, Ops);
- break;
-
- }
case ISD::CopyToReg: {
const SITargetLowering& Lowering =
*static_cast<const SITargetLowering*>(getTargetLowering());