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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-10-08 18:40:44 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-10-15 15:40:44 +0000 |
| commit | 180a9d8a7c4a81bc2f104fb11b32db87ff27bbff (patch) | |
| tree | 91f27b3153c09d7c54d24aa81709ecfe3a6f1824 | |
| parent | da264b5bdfb0d3edabfcd9e059663a37dd2c81b8 (diff) | |
XXX: SCALAR branch
| -rw-r--r-- | lib/Target/AMDGPU/SIRegisterInfo.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/AMDGPU/SIRegisterInfo.cpp b/lib/Target/AMDGPU/SIRegisterInfo.cpp index 26cfa203cf7..687025f70d8 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -332,6 +332,7 @@ const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const { assert(!TargetRegisterInfo::isVirtualRegister(Reg)); static const TargetRegisterClass *BaseClasses[] = { + &AMDGPU::SCC_CLASSRegClass, &AMDGPU::VGPR_32RegClass, &AMDGPU::SReg_32RegClass, &AMDGPU::VReg_64RegClass, @@ -357,6 +358,8 @@ const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const { // TargetRegisterClass to mark which classes are VGPRs to make this trivial. bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const { switch (RC->getSize()) { + case 0: return false; + case 1: return false; case 4: return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) != nullptr; case 8: |