XXX: BUffer

1 files changed, 19 insertions, 12 deletions

diff --git a/lib/Target/R600/SISchedule.td b/lib/Target/R600/SISchedule.td
index 9b1f676020b..78291074f7a 100644
--- a/lib/Target/R600/SISchedule.td
+++ b/lib/Target/R600/SISchedule.td
@@ -27,22 +27,29 @@ def WriteFloatFMA   : SchedWrite;
 def WriteDouble     : SchedWrite;
 def WriteDoubleAdd  : SchedWrite;
 
-def SIFullSpeedModel : SchedMachineModel;
-def SIQuarterSpeedModel : SchedMachineModel;
-
-// BufferSize = 0 means the processors are in-order.
-let BufferSize = 0 in {
+class SISchedMachineModel : SchedMachineModel {
+  // This is a somewhat arbitrary value.  It was choosen because it is
+  // half the size of the memory resource buffers (SALU, LGKM, VMEM).
+  // Since this is an out of order processor, we need to set this to
+  // something greater than 1.
+  let MicroOpBufferSize = 32;
+}
 
-// XXX: Are the resource counts correct?
-def HWBranch : ProcResource<1>;
-def HWExport : ProcResource<7>;   // Taken from S_WAITCNT
-def HWLGKM   : ProcResource<31>;  // Taken from S_WAITCNT
-def HWSALU   : ProcResource<1>;
-def HWVMEM   : ProcResource<15>;  // Taken from S_WAITCNT
-def HWVALU   : ProcResource<1>;
+def SIFullSpeedModel : SISchedMachineModel;
+def SIQuarterSpeedModel : SISchedMachineModel;
 
+class SIProcResource <int buffer_size> : ProcResource <1> {
+  let BufferSize = buffer_size;
 }
 
+// XXX: Are the resource counts correct?
+def HWBranch : SIProcResource<1>;
+def HWExport : SIProcResource<8>;   // Taken from S_WAITCNT
+def HWLGKM   : SIProcResource<32>;  // Taken from S_WAITCNT
+def HWSALU   : SIProcResource<1>;
+def HWVMEM   : SIProcResource<16>;  // Taken from S_WAITCNT
+def HWVALU   : SIProcResource<1>;
+
 class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
                  int latency> : WriteRes<write, resources> {
   let Latency = latency;