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authorTom Stellard <thomas.stellard@amd.com>2014-05-15 14:41:57 +0000
committerTom Stellard <thomas.stellard@amd.com>2014-05-15 14:41:57 +0000
commit29d4ed329e710bc78e537f295223448525aa486c (patch)
treeb23154ec4ae2be72a25cf06613f2df365b5a5be0
parent704fe35d8803ad6e6d09cf3a67659f04b464c458 (diff)
R600/SI: Stop using VSrc_* as the default register class for types.
We now use SReg_* for integer types and VReg_* for floating-point types. This should help simplify the SIFixSGPRCopies pass and no longer causes ISel to insert a COPY after termiator instuctions that output a value. This change is covered by exisitng tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208888 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/R600/SIISelLowering.cpp49
-rw-r--r--lib/Target/R600/SIInstructions.td25
2 files changed, 11 insertions, 63 deletions
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
index da8aa5b7a98..24eb24e4fac 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -30,20 +30,20 @@ using namespace llvm;
SITargetLowering::SITargetLowering(TargetMachine &TM) :
AMDGPUTargetLowering(TM) {
addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
- addRegisterClass(MVT::i64, &AMDGPU::VSrc_64RegClass);
+ addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
- addRegisterClass(MVT::f32, &AMDGPU::VSrc_32RegClass);
+ addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
- addRegisterClass(MVT::f64, &AMDGPU::VSrc_64RegClass);
- addRegisterClass(MVT::v2i32, &AMDGPU::VSrc_64RegClass);
- addRegisterClass(MVT::v2f32, &AMDGPU::VSrc_64RegClass);
+ addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
+ addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
+ addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
- addRegisterClass(MVT::v4i32, &AMDGPU::VSrc_128RegClass);
- addRegisterClass(MVT::v4f32, &AMDGPU::VSrc_128RegClass);
+ addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
+ addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
@@ -444,35 +444,6 @@ SDValue SITargetLowering::LowerFormalArguments(
return Chain;
}
-/// Usually ISel will insert a copy between terminator insturction that output
-/// a value and the S_BRANCH* at the end of the block. This causes
-/// MachineBasicBlock::getFirstTerminator() to return the incorrect value,
-/// so we want to make sure there are no copies between terminators at the
-/// end of blocks.
-static void LowerTerminatorWithOutput(unsigned Opcode, MachineBasicBlock *BB,
- MachineInstr *MI,
- const TargetInstrInfo *TII,
- MachineRegisterInfo &MRI) {
- unsigned DstReg = MI->getOperand(0).getReg();
- // Usually ISel will insert a copy between the SI_IF_NON_TERM instruction
- // and the S_BRANCH* terminator. We want to replace SI_IF_NO_TERM with
- // SI_IF and we can't have any instructions between S_BRANCH* and SI_IF,
- // since they are both terminators
- assert(MRI.hasOneUse(DstReg));
- MachineOperand &Use = *MRI.use_begin(DstReg);
- MachineInstr *UseMI = Use.getParent();
- assert(UseMI->getOpcode() == AMDGPU::COPY);
-
- MRI.replaceRegWith(UseMI->getOperand(0).getReg(), DstReg);
- UseMI->eraseFromParent();
- BuildMI(*BB, BB->getFirstTerminator(), MI->getDebugLoc(),
- TII->get(Opcode))
- .addOperand(MI->getOperand(0))
- .addOperand(MI->getOperand(1))
- .addOperand(MI->getOperand(2));
- MI->eraseFromParent();
-}
-
MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MachineInstr * MI, MachineBasicBlock * BB) const {
@@ -510,12 +481,6 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MI->eraseFromParent();
break;
}
- case AMDGPU::SI_IF_NON_TERM:
- LowerTerminatorWithOutput(AMDGPU::SI_IF, BB, MI, TII, MRI);
- break;
- case AMDGPU::SI_ELSE_NON_TERM:
- LowerTerminatorWithOutput(AMDGPU::SI_ELSE, BB, MI, TII, MRI);
- break;
case AMDGPU::V_SUB_F64:
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64),
MI->getOperand(0).getReg())
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
index ad26c9b84ff..0d23141aa5d 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -1431,37 +1431,20 @@ def LOAD_CONST : AMDGPUShaderInst <
let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
Uses = [EXEC], Defs = [EXEC] in {
-let usesCustomInserter = 1 in {
-
-def SI_IF_NON_TERM : InstSI <
- (outs SReg_64:$dst),
- (ins SReg_64:$vcc, brtarget:$target), "",
- [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
->;
-
-def SI_ELSE_NON_TERM : InstSI <
- (outs SReg_64:$dst),
- (ins SReg_64:$src, brtarget:$target),
- "",
- [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
-> {
- let Constraints = "$src = $dst";
-}
-
-} // usesCustomInserter = 1
-
let isBranch = 1, isTerminator = 1 in {
def SI_IF: InstSI <
(outs SReg_64:$dst),
(ins SReg_64:$vcc, brtarget:$target),
- "", []
+ "",
+ [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
>;
def SI_ELSE : InstSI <
(outs SReg_64:$dst),
(ins SReg_64:$src, brtarget:$target),
- "", []
+ "",
+ [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
> {
let Constraints = "$src = $dst";
}