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authorTim Northover <Tim.Northover@arm.com>2013-04-19 09:58:09 +0000
committerTim Northover <Tim.Northover@arm.com>2013-04-19 09:58:09 +0000
commit4521019c6fd23680c583abe086067fc1c569bad1 (patch)
treefb57e00a4c18c886095fdb0eb51cce95e8d00fe4
parenta7e3701658632f9e852b4ea3a2f42ae2b69e51cf (diff)
ARM: permit "sp" in ARM variants of MOVW/MOVT instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179847 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/Disassembler/ARMDisassembler.cpp5
-rw-r--r--test/MC/Disassembler/ARM/basic-arm-instructions.txt6
2 files changed, 9 insertions, 2 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 9c81eceb40f..631168b1539 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -1998,9 +1998,10 @@ static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
if (Inst.getOpcode() == ARM::MOVTi16)
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
+
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt
index 477ba728b39..505ecad9d3a 100644
--- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt
+++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt
@@ -707,8 +707,10 @@
# CHECK: mov r3, #7
# CHECK: mov r4, #4080
# CHECK: mov r5, #16711680
+# CHECK: mov sp, #35
# CHECK: movw r6, #65535
# CHECK: movw r9, #65535
+# CHECK: movw sp, #1193
# CHECK: movs r3, #7
# CHECK: moveq r4, #4080
# CHECK: movseq r5, #16711680
@@ -716,8 +718,10 @@
0x07 0x30 0xa0 0xe3
0xff 0x4e 0xa0 0xe3
0xff 0x58 0xa0 0xe3
+0x23 0xd0 0xa0 0xe3
0xff 0x6f 0x0f 0xe3
0xff 0x9f 0x0f 0xe3
+0xa9 0xd4 0x00 0xe3
0x07 0x30 0xb0 0xe3
0xff 0x4e 0xa0 0x03
0xff 0x58 0xb0 0x03
@@ -740,10 +744,12 @@
#------------------------------------------------------------------------------
# CHECK: movt r3, #7
# CHECK: movt r6, #65535
+# CHECK: movt sp, #3397
# CHECK: movteq r4, #4080
0x07 0x30 0x40 0xe3
0xff 0x6f 0x4f 0xe3
+0x45 0xdd 0x40 0xe3
0xf0 0x4f 0x40 0x03