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authorAkira Hatanaka <ahatanaka@mips.com>2012-04-25 01:24:52 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2012-04-25 01:24:52 +0000
commit25052f4077503d030e65a025b348c5f1e9ffb616 (patch)
treee3c589ecf156859112727f861c48e5d01275623d
parent23d59c2fb847f1869b72bcbda67052ac6b2aaee9 (diff)
Do not use $gp as a dedicated global register if the target ABI is not O32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155522 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/Mips/MipsMachineFunction.cpp4
-rw-r--r--test/CodeGen/Mips/2010-07-20-Switch.ll3
-rwxr-xr-xtest/CodeGen/Mips/cmov.ll8
3 files changed, 8 insertions, 7 deletions
diff --git a/lib/Target/Mips/MipsMachineFunction.cpp b/lib/Target/Mips/MipsMachineFunction.cpp
index 9d3a27b518f..8535b290b43 100644
--- a/lib/Target/Mips/MipsMachineFunction.cpp
+++ b/lib/Target/Mips/MipsMachineFunction.cpp
@@ -37,8 +37,8 @@ unsigned MipsFunctionInfo::getGlobalBaseReg() {
const MipsSubtarget &ST = MF.getTarget().getSubtarget<MipsSubtarget>();
- if (FixGlobalBaseReg) // $gp is the global base register.
- return GlobalBaseReg = ST.isABI_N64() ? Mips::GP_64 : Mips::GP;
+ if (FixGlobalBaseReg && ST.isABI_O32()) // $gp is the global base register.
+ return GlobalBaseReg = Mips::GP;
const TargetRegisterClass *RC = ST.isABI_N64() ?
(const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
diff --git a/test/CodeGen/Mips/2010-07-20-Switch.ll b/test/CodeGen/Mips/2010-07-20-Switch.ll
index aaf6767a3bd..a9f1d0b8ce7 100644
--- a/test/CodeGen/Mips/2010-07-20-Switch.ll
+++ b/test/CodeGen/Mips/2010-07-20-Switch.ll
@@ -15,10 +15,11 @@ entry:
; PIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2
; PIC-O32: addu $[[R1:[0-9]+]], ${{[0-9]+}}, $gp
; PIC-O32: jr $[[R1]]
+; PIC-N64: daddiu $[[R2:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(main)))
; PIC-N64: ld $[[R0:[0-9]+]], %got_page($JTI0_0)
; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($JTI0_0)
; PIC-N64: dsll ${{[0-9]+}}, ${{[0-9]+}}, 3
-; PIC-N64: daddu $[[R1:[0-9]+]], ${{[0-9]+}}, $gp
+; PIC-N64: daddu $[[R1:[0-9]+]], ${{[0-9]+}}, $[[R2]]
; PIC-N64: jr $[[R1]]
switch i32 %0, label %bb4 [
i32 0, label %bb5
diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll
index 03254a9a799..86bf3370801 100755
--- a/test/CodeGen/Mips/cmov.ll
+++ b/test/CodeGen/Mips/cmov.ll
@@ -7,8 +7,8 @@
; O32: lw ${{[0-9]+}}, %got(i3)($gp)
; O32: addiu ${{[0-9]+}}, $gp, %got(i1)
-; N64: ld ${{[0-9]+}}, %got_disp(i3)($gp)
-; N64: daddiu ${{[0-9]+}}, $gp, %got_disp(i1)
+; N64: ld ${{[0-9]+}}, %got_disp(i3)
+; N64: daddiu ${{[0-9]+}}, ${{[0-9]+}}, %got_disp(i1)
define i32* @cmov1(i32 %s) nounwind readonly {
entry:
%tobool = icmp ne i32 %s, 0
@@ -25,8 +25,8 @@ entry:
; O32: addiu $[[R0:[0-9]+]], $gp, %got(c)
; O32: movn $[[R1]], $[[R0]], ${{[0-9]+}}
; N64: cmov2:
-; N64: daddiu $[[R1:[0-9]+]], $gp, %got_disp(d)
-; N64: daddiu $[[R0:[0-9]+]], $gp, %got_disp(c)
+; N64: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
+; N64: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)
; N64: movn $[[R1]], $[[R0]], ${{[0-9]+}}
define i32 @cmov2(i32 %s) nounwind readonly {
entry: