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authorTom Stellard <thomas.stellard@amd.com>2012-03-27 14:04:54 -0400
committerTom Stellard <thomas.stellard@amd.com>2012-04-25 14:44:18 -0400
commit1e7f745dc59b5a8cb17b8546fe8fd399bebe0e4c (patch)
tree4ba24e785ac09e8711ce00965f138ed63f2d0472
parent6503c05aafd84388cacbf9fef76e7a0f4207c439 (diff)
test/CodeGen/R600: Add some basic tests
-rw-r--r--test/CodeGen/R600/fadd.ll18
-rw-r--r--test/CodeGen/R600/fadd.ll.checkbin0 -> 48 bytes
-rw-r--r--test/CodeGen/R600/fmul.ll18
-rw-r--r--test/CodeGen/R600/fmul.ll.checkbin0 -> 48 bytes
-rw-r--r--test/CodeGen/R600/fsub.ll18
-rw-r--r--test/CodeGen/R600/fsub.ll.checkbin0 -> 48 bytes
-rw-r--r--test/CodeGen/R600/lit.local.cfg13
-rw-r--r--test/CodeGen/R600/llvm.AMDGPU.cos.ll18
-rw-r--r--test/CodeGen/R600/llvm.AMDGPU.cos.ll.checkbin0 -> 192 bytes
-rw-r--r--test/CodeGen/R600/llvm.AMDGPU.floor.ll18
-rw-r--r--test/CodeGen/R600/llvm.AMDGPU.floor.ll.checkbin0 -> 48 bytes
-rw-r--r--test/CodeGen/R600/llvm.AMDGPU.mul.ll19
-rw-r--r--test/CodeGen/R600/llvm.AMDGPU.mul.ll.checkbin0 -> 48 bytes
-rw-r--r--test/CodeGen/R600/llvm.AMDGPU.pow.ll19
-rw-r--r--test/CodeGen/R600/llvm.AMDGPU.pow.ll.checkbin0 -> 144 bytes
-rw-r--r--test/CodeGen/R600/llvm.AMDGPU.rcp.ll18
-rw-r--r--test/CodeGen/R600/llvm.AMDGPU.rcp.ll.checkbin0 -> 48 bytes
-rw-r--r--test/CodeGen/R600/llvm.AMDGPU.sin.ll18
-rw-r--r--test/CodeGen/R600/llvm.AMDGPU.sin.ll.checkbin0 -> 192 bytes
-rw-r--r--test/CodeGen/R600/llvm.AMDGPU.trunc.ll18
-rw-r--r--test/CodeGen/R600/llvm.AMDGPU.trunc.ll.checkbin0 -> 48 bytes
-rw-r--r--test/CodeGen/R600/llvm.AMDIL.fabs..ll18
-rw-r--r--test/CodeGen/R600/llvm.AMDIL.fabs..ll.checkbin0 -> 48 bytes
-rw-r--r--test/CodeGen/R600/llvm.AMDIL.max..ll19
-rw-r--r--test/CodeGen/R600/llvm.AMDIL.max..ll.checkbin0 -> 48 bytes
-rw-r--r--test/CodeGen/R600/llvm.AMDIL.min..ll19
-rw-r--r--test/CodeGen/R600/llvm.AMDIL.min..ll.checkbin0 -> 48 bytes
27 files changed, 251 insertions, 0 deletions
diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll
new file mode 100644
index 00000000000..5bdc81e34fc
--- /dev/null
+++ b/test/CodeGen/R600/fadd.ll
@@ -0,0 +1,18 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+ %r0 = call float @llvm.R600.load.input(i32 0)
+ %r1 = call float @llvm.R600.load.input(i32 1)
+ %r2 = fadd float %r0, %r1
+ %r3 = call float @llvm.AMDGPU.store.output(float %r2, i32 0)
+ call void @llvm.AMDGPU.export.reg(float %r3)
+ ret void
+}
+
+declare void @llvm.AMDGPU.export.reg(float)
+
+declare float @llvm.R600.load.input(i32)
+
+declare float @llvm.AMDGPU.store.output(float, i32)
+
diff --git a/test/CodeGen/R600/fadd.ll.check b/test/CodeGen/R600/fadd.ll.check
new file mode 100644
index 00000000000..886082f2262
--- /dev/null
+++ b/test/CodeGen/R600/fadd.ll.check
Binary files differ
diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll
new file mode 100644
index 00000000000..4d48ff3c0b2
--- /dev/null
+++ b/test/CodeGen/R600/fmul.ll
@@ -0,0 +1,18 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+ %r0 = call float @llvm.R600.load.input(i32 0)
+ %r1 = call float @llvm.R600.load.input(i32 1)
+ %r2 = fmul float %r0, %r1
+ %r3 = call float @llvm.AMDGPU.store.output(float %r2, i32 0)
+ call void @llvm.AMDGPU.export.reg(float %r3)
+ ret void
+}
+
+declare void @llvm.AMDGPU.export.reg(float)
+
+declare float @llvm.R600.load.input(i32)
+
+declare float @llvm.AMDGPU.store.output(float, i32)
+
diff --git a/test/CodeGen/R600/fmul.ll.check b/test/CodeGen/R600/fmul.ll.check
new file mode 100644
index 00000000000..9ba36ccb741
--- /dev/null
+++ b/test/CodeGen/R600/fmul.ll.check
Binary files differ
diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll
new file mode 100644
index 00000000000..a380647acd9
--- /dev/null
+++ b/test/CodeGen/R600/fsub.ll
@@ -0,0 +1,18 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+ %r0 = call float @llvm.R600.load.input(i32 0)
+ %r1 = call float @llvm.R600.load.input(i32 1)
+ %r2 = fsub float %r0, %r1
+ %r3 = call float @llvm.AMDGPU.store.output(float %r2, i32 0)
+ call void @llvm.AMDGPU.export.reg(float %r3)
+ ret void
+}
+
+declare void @llvm.AMDGPU.export.reg(float)
+
+declare float @llvm.R600.load.input(i32)
+
+declare float @llvm.AMDGPU.store.output(float, i32)
+
diff --git a/test/CodeGen/R600/fsub.ll.check b/test/CodeGen/R600/fsub.ll.check
new file mode 100644
index 00000000000..f2209118927
--- /dev/null
+++ b/test/CodeGen/R600/fsub.ll.check
Binary files differ
diff --git a/test/CodeGen/R600/lit.local.cfg b/test/CodeGen/R600/lit.local.cfg
new file mode 100644
index 00000000000..78d16d177f9
--- /dev/null
+++ b/test/CodeGen/R600/lit.local.cfg
@@ -0,0 +1,13 @@
+config.suffixes = ['.ll', '.c', '.cpp']
+
+def getRoot(config):
+ if not config.parent:
+ return config
+ return getRoot(config.parent)
+
+root = getRoot(config)
+
+targets = set(root.targets_to_build.split())
+if not 'AMDIL' in targets:
+ config.unsupported = True
+
diff --git a/test/CodeGen/R600/llvm.AMDGPU.cos.ll b/test/CodeGen/R600/llvm.AMDGPU.cos.ll
new file mode 100644
index 00000000000..f2b562582ca
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.cos.ll
@@ -0,0 +1,18 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+ %r0 = call float @llvm.R600.load.input(i32 0)
+ %r1 = call float @llvm.AMDGPU.cos( float %r0)
+ %r2 = call float @llvm.AMDGPU.store.output(float %r1, i32 0)
+ call void @llvm.AMDGPU.export.reg(float %r2)
+ ret void
+}
+
+declare void @llvm.AMDGPU.export.reg(float)
+
+declare float @llvm.R600.load.input(i32)
+
+declare float @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.cos(float ) \ No newline at end of file
diff --git a/test/CodeGen/R600/llvm.AMDGPU.cos.ll.check b/test/CodeGen/R600/llvm.AMDGPU.cos.ll.check
new file mode 100644
index 00000000000..1c3770101b0
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.cos.ll.check
Binary files differ
diff --git a/test/CodeGen/R600/llvm.AMDGPU.floor.ll b/test/CodeGen/R600/llvm.AMDGPU.floor.ll
new file mode 100644
index 00000000000..a0c17ce7650
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.floor.ll
@@ -0,0 +1,18 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+ %r0 = call float @llvm.R600.load.input(i32 0)
+ %r1 = call float @llvm.AMDGPU.floor( float %r0)
+ %r2 = call float @llvm.AMDGPU.store.output(float %r1, i32 0)
+ call void @llvm.AMDGPU.export.reg(float %r2)
+ ret void
+}
+
+declare void @llvm.AMDGPU.export.reg(float)
+
+declare float @llvm.R600.load.input(i32)
+
+declare float @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.floor(float ) \ No newline at end of file
diff --git a/test/CodeGen/R600/llvm.AMDGPU.floor.ll.check b/test/CodeGen/R600/llvm.AMDGPU.floor.ll.check
new file mode 100644
index 00000000000..324c10d94c8
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.floor.ll.check
Binary files differ
diff --git a/test/CodeGen/R600/llvm.AMDGPU.mul.ll b/test/CodeGen/R600/llvm.AMDGPU.mul.ll
new file mode 100644
index 00000000000..a6b0e3f850e
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.mul.ll
@@ -0,0 +1,19 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+ %r0 = call float @llvm.R600.load.input(i32 0)
+ %r1 = call float @llvm.R600.load.input(i32 1)
+ %r2 = call float @llvm.AMDGPU.mul( float %r0, float %r1)
+ %r3 = call float @llvm.AMDGPU.store.output(float %r2, i32 0)
+ call void @llvm.AMDGPU.export.reg(float %r3)
+ ret void
+}
+
+declare void @llvm.AMDGPU.export.reg(float)
+
+declare float @llvm.R600.load.input(i32)
+
+declare float @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.mul(float ,float ) \ No newline at end of file
diff --git a/test/CodeGen/R600/llvm.AMDGPU.mul.ll.check b/test/CodeGen/R600/llvm.AMDGPU.mul.ll.check
new file mode 100644
index 00000000000..0a79cbaf263
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.mul.ll.check
Binary files differ
diff --git a/test/CodeGen/R600/llvm.AMDGPU.pow.ll b/test/CodeGen/R600/llvm.AMDGPU.pow.ll
new file mode 100644
index 00000000000..fe690334240
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.pow.ll
@@ -0,0 +1,19 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+ %r0 = call float @llvm.R600.load.input(i32 0)
+ %r1 = call float @llvm.R600.load.input(i32 1)
+ %r2 = call float @llvm.AMDGPU.pow( float %r0, float %r1)
+ %r3 = call float @llvm.AMDGPU.store.output(float %r2, i32 0)
+ call void @llvm.AMDGPU.export.reg(float %r3)
+ ret void
+}
+
+declare void @llvm.AMDGPU.export.reg(float)
+
+declare float @llvm.R600.load.input(i32)
+
+declare float @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.pow(float ,float ) \ No newline at end of file
diff --git a/test/CodeGen/R600/llvm.AMDGPU.pow.ll.check b/test/CodeGen/R600/llvm.AMDGPU.pow.ll.check
new file mode 100644
index 00000000000..94af645419b
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.pow.ll.check
Binary files differ
diff --git a/test/CodeGen/R600/llvm.AMDGPU.rcp.ll b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll
new file mode 100644
index 00000000000..ced64eac083
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll
@@ -0,0 +1,18 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+ %r0 = call float @llvm.R600.load.input(i32 0)
+ %r1 = call float @llvm.AMDGPU.rcp( float %r0)
+ %r2 = call float @llvm.AMDGPU.store.output(float %r1, i32 0)
+ call void @llvm.AMDGPU.export.reg(float %r2)
+ ret void
+}
+
+declare void @llvm.AMDGPU.export.reg(float)
+
+declare float @llvm.R600.load.input(i32)
+
+declare float @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.rcp(float ) \ No newline at end of file
diff --git a/test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check
new file mode 100644
index 00000000000..75fe90c5189
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check
Binary files differ
diff --git a/test/CodeGen/R600/llvm.AMDGPU.sin.ll b/test/CodeGen/R600/llvm.AMDGPU.sin.ll
new file mode 100644
index 00000000000..18df0ab0e6b
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.sin.ll
@@ -0,0 +1,18 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+ %r0 = call float @llvm.R600.load.input(i32 0)
+ %r1 = call float @llvm.AMDGPU.sin( float %r0)
+ %r2 = call float @llvm.AMDGPU.store.output(float %r1, i32 0)
+ call void @llvm.AMDGPU.export.reg(float %r2)
+ ret void
+}
+
+declare void @llvm.AMDGPU.export.reg(float)
+
+declare float @llvm.R600.load.input(i32)
+
+declare float @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.sin(float ) \ No newline at end of file
diff --git a/test/CodeGen/R600/llvm.AMDGPU.sin.ll.check b/test/CodeGen/R600/llvm.AMDGPU.sin.ll.check
new file mode 100644
index 00000000000..77dce6ab45b
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.sin.ll.check
Binary files differ
diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
new file mode 100644
index 00000000000..dfe42eea6bb
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
@@ -0,0 +1,18 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+ %r0 = call float @llvm.R600.load.input(i32 0)
+ %r1 = call float @llvm.AMDGPU.trunc( float %r0)
+ %r2 = call float @llvm.AMDGPU.store.output(float %r1, i32 0)
+ call void @llvm.AMDGPU.export.reg(float %r2)
+ ret void
+}
+
+declare void @llvm.AMDGPU.export.reg(float)
+
+declare float @llvm.R600.load.input(i32)
+
+declare float @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.trunc(float ) \ No newline at end of file
diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check
new file mode 100644
index 00000000000..f9c93b3def5
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check
Binary files differ
diff --git a/test/CodeGen/R600/llvm.AMDIL.fabs..ll b/test/CodeGen/R600/llvm.AMDIL.fabs..ll
new file mode 100644
index 00000000000..36654cb6be2
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDIL.fabs..ll
@@ -0,0 +1,18 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+ %r0 = call float @llvm.R600.load.input(i32 0)
+ %r1 = call float @llvm.AMDIL.fabs.( float %r0)
+ %r2 = call float @llvm.AMDGPU.store.output(float %r1, i32 0)
+ call void @llvm.AMDGPU.export.reg(float %r2)
+ ret void
+}
+
+declare void @llvm.AMDGPU.export.reg(float)
+
+declare float @llvm.R600.load.input(i32)
+
+declare float @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDIL.fabs.(float ) \ No newline at end of file
diff --git a/test/CodeGen/R600/llvm.AMDIL.fabs..ll.check b/test/CodeGen/R600/llvm.AMDIL.fabs..ll.check
new file mode 100644
index 00000000000..ff3124ca903
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDIL.fabs..ll.check
Binary files differ
diff --git a/test/CodeGen/R600/llvm.AMDIL.max..ll b/test/CodeGen/R600/llvm.AMDIL.max..ll
new file mode 100644
index 00000000000..e5f7ef89cb6
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDIL.max..ll
@@ -0,0 +1,19 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+ %r0 = call float @llvm.R600.load.input(i32 0)
+ %r1 = call float @llvm.R600.load.input(i32 1)
+ %r2 = call float @llvm.AMDIL.max.( float %r0, float %r1)
+ %r3 = call float @llvm.AMDGPU.store.output(float %r2, i32 0)
+ call void @llvm.AMDGPU.export.reg(float %r3)
+ ret void
+}
+
+declare void @llvm.AMDGPU.export.reg(float)
+
+declare float @llvm.R600.load.input(i32)
+
+declare float @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDIL.max.(float ,float ) \ No newline at end of file
diff --git a/test/CodeGen/R600/llvm.AMDIL.max..ll.check b/test/CodeGen/R600/llvm.AMDIL.max..ll.check
new file mode 100644
index 00000000000..9ae4070fdc8
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDIL.max..ll.check
Binary files differ
diff --git a/test/CodeGen/R600/llvm.AMDIL.min..ll b/test/CodeGen/R600/llvm.AMDIL.min..ll
new file mode 100644
index 00000000000..ac0e694e99a
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDIL.min..ll
@@ -0,0 +1,19 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+ %r0 = call float @llvm.R600.load.input(i32 0)
+ %r1 = call float @llvm.R600.load.input(i32 1)
+ %r2 = call float @llvm.AMDIL.min.( float %r0, float %r1)
+ %r3 = call float @llvm.AMDGPU.store.output(float %r2, i32 0)
+ call void @llvm.AMDGPU.export.reg(float %r3)
+ ret void
+}
+
+declare void @llvm.AMDGPU.export.reg(float)
+
+declare float @llvm.R600.load.input(i32)
+
+declare float @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDIL.min.(float ,float ) \ No newline at end of file
diff --git a/test/CodeGen/R600/llvm.AMDIL.min..ll.check b/test/CodeGen/R600/llvm.AMDIL.min..ll.check
new file mode 100644
index 00000000000..3d343bdea61
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDIL.min..ll.check
Binary files differ