diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2012-10-16 14:16:20 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2012-10-18 15:53:55 +0000 |
| commit | b70962c3423d1e9662e34cbe0017e98fa4468522 (patch) | |
| tree | 71fdca1f1e12aae0f37afb45396ece0c23157478 | |
| parent | 4353bda5e2e5924e10d005242ba1a8b985254459 (diff) | |
R600: Emit CONTINUE instructions correctly
The finalizer in mesa was incorrectly handling conditional continue
instructions and the backend wasn't generating code for the unconditional
version at all.
This patch enables code generation for the unconditional continue and
disables it for conditional continue.
| -rw-r--r-- | lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp index f5e9af19179..dd2a511fa8a 100644 --- a/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp @@ -540,8 +540,7 @@ void R600MCCodeEmitter::EmitFCInstr(const MCInst &MI, raw_ostream &OS) const { case AMDGPU::BREAK_LOGICALZ_i32: instr = FC_BREAK_Z_INT; break; - case AMDGPU::CONTINUE_LOGICALNZ_f32: - case AMDGPU::CONTINUE_LOGICALNZ_i32: + case AMDGPU::CONTINUE: instr = FC_CONTINUE; break; case AMDGPU::IF_LOGICALNZ_f32: @@ -633,7 +632,7 @@ bool R600MCCodeEmitter::isFCOp(unsigned opcode) const { case AMDGPU::BREAK_LOGICALNZ_i32: case AMDGPU::BREAK_LOGICALZ_i32: case AMDGPU::BREAK_LOGICALNZ_f32: - case AMDGPU::CONTINUE_LOGICALNZ_f32: + case AMDGPU::CONTINUE: case AMDGPU::IF_LOGICALNZ_i32: case AMDGPU::IF_LOGICALZ_f32: case AMDGPU::ELSE: |