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authorTom Stellard <thomas.stellard@amd.com>2014-11-25 15:19:25 +0000
committerTom Stellard <thomas.stellard@amd.com>2014-11-25 15:19:25 +0000
commit3ac6db2dba3799046ee086fd885655c22bb2420f (patch)
tree9ec301ba9d3b56555813f96d886ef921be9ae7b1
parent078efa769933f1cc569b128bfad82170378d2cf8 (diff)
TargetRegisterInfo: Add target query subRegWriteClobbersSuperReg()
This allows targets to specify wheather or not is is possible to write to a sub-register without affecting other sub-registers in the same super-reg.
-rw-r--r--include/llvm/Target/TargetRegisterInfo.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h
index 16b72a98db0..88157f89310 100644
--- a/include/llvm/Target/TargetRegisterInfo.h
+++ b/include/llvm/Target/TargetRegisterInfo.h
@@ -818,6 +818,19 @@ public:
const TargetRegisterClass *NewRC) const
{ return true; }
+ /// \returns true if a write to \p SubIdx clobbers values in non-overlaping
+ /// sub-registers of this super register.
+ /// For Example:
+ ///
+ /// %vreg1:sub1<def> = LOAD %vreg0, Reg64:%vreg1 Reg64:%vreg0
+ ///
+ /// If the LOAD instruction modifies the value of vreg1:sub0, then this
+ /// function should return true.
+ virtual bool subRegWriteClobbersSuperReg(const TargetRegisterClass *RC,
+ unsigned SubIdx) const {
+ return true;
+ }
+
//===--------------------------------------------------------------------===//
/// Debug information queries.