diff options
| author | Michel Dänzer <michel.daenzer@amd.com> | 2012-11-14 12:38:58 +0100 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2012-11-16 17:04:33 -0500 |
| commit | 162a9bfb0575da2bf892026721fb50b06888348b (patch) | |
| tree | 9707b26ae77e26d7c168d1b9b978b9ebac53ff92 | |
| parent | 76d0982235ed4a091cdab5b9f96ea49ef22f4805 (diff) | |
AMDGPU: Don't allow using SI SGPRs 102 and 103 directly.
Two SGPRs are used for VCC, so it's not possible to use these and VCC
together.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
| -rw-r--r-- | lib/Target/AMDGPU/SIRegisterInfo.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/AMDGPU/SIRegisterInfo.td b/lib/Target/AMDGPU/SIRegisterInfo.td index a3d91ae0831..e52311ab8a9 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/lib/Target/AMDGPU/SIRegisterInfo.td @@ -65,12 +65,12 @@ def SAMPLE_COVERAGE : SIReg <"SAMPLE_COVERAGE">; def POS_FIXED_PT : SIReg <"POS_FIXED_PT">; // SGPR 32-bit registers -foreach Index = 0-103 in { +foreach Index = 0-101 in { def SGPR#Index : SGPR_32 <Index, "SGPR"#Index>; } def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32, - (add (sequence "SGPR%u", 0, 103))>; + (add (sequence "SGPR%u", 0, 101))>; // SGPR 64-bit registers def SGPR_64 : RegisterTuples<[low, high], |