R600: Use native operands for KILLGT instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166335 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 29 insertions, 38 deletions

diff --git a/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
index f3d80a39c3c..5c12c18fd47 100644
--- a/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+++ b/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
@@ -58,11 +58,6 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   AMDGPUMCInstLower MCInstLowering;
 
-  // Ignore placeholder instructions:
-  if (MI->getOpcode() == AMDGPU::MASK_WRITE) {
-    return;
-  }
-
   if (MI->isBundle()) {
     const MachineBasicBlock *MBB = MI->getParent();
     MachineBasicBlock::const_instr_iterator I = MI;
diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp
index b05089c3c2c..a7cb0101241 100644
--- a/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -124,8 +124,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
       assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
       MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
       TII->addFlag(defInstr, 0, MO_FLAG_MASK);
-      // Return early so the instruction is not erased
-      return BB;
+      break;
     }
 
   case AMDGPU::MOV_IMM_F32:
diff --git a/lib/Target/AMDGPU/R600InstrInfo.cpp b/lib/Target/AMDGPU/R600InstrInfo.cpp
index 499b7066709..49169d7816e 100644
--- a/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -111,7 +111,6 @@ bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const
   switch (Opcode) {
   default: return false;
   case AMDGPU::RETURN:
-  case AMDGPU::MASK_WRITE:
   case AMDGPU::RESERVE_REG:
     return true;
   }
@@ -357,7 +356,16 @@ R600InstrInfo::isPredicated(const MachineInstr *MI) const
 bool
 R600InstrInfo::isPredicable(MachineInstr *MI) const
 {
-  return AMDGPUInstrInfo::isPredicable(MI);
+  // XXX: KILL* instructions can be predicated, but they must be the last
+  // instruction in a clause, so this means any instructions after them cannot
+  // be predicated.  Until we have proper support for instruction clauses in the
+  // backend, we will mark KILL* instructions as unpredicable.
+
+  if (MI->getOpcode() == AMDGPU::KILLGT) {
+    return false;
+  } else {
+    return AMDGPUInstrInfo::isPredicable(MI);
+  }
 }
 
 
diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td
index 11c29f04f5e..7cc74e82155 100644
--- a/lib/Target/AMDGPU/R600Instructions.td
+++ b/lib/Target/AMDGPU/R600Instructions.td
@@ -551,22 +551,11 @@ def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
 
-def KILLGT : InstR600 <0x2D,
-          (outs R600_Reg32:$dst),
-          (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags, R600_Pred:$p,
-               variable_ops),
-          "KILLGT $dst, $src0, $src1, $flags ($p)",
-          [],
-          NullALU>{
-  let FlagOperandIdx = 3;
-  bits<7> dst;
-  bits<9> src0;
-  bits<9> src1;
-  let Inst{8-0}   = src0;
-  let Inst{21-13} = src1;
-  let Inst{49-39} = op_code;
-  let Inst{59-53} = dst;
-}
+let hasSideEffects = 1 in {
+
+def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
+
+} // end hasSideEffects
 
 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
@@ -1343,6 +1332,17 @@ def JUMP : InstR600 <0x10,
 
 let usesCustomInserter = 1 in {
 
+let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
+
+def MASK_WRITE : AMDGPUShaderInst <
+    (outs),
+    (ins R600_Reg32:$src),
+    "MASK_WRITE $src",
+    []
+>;
+
+} // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
+
 def R600_LOAD_CONST : AMDGPUShaderInst <
   (outs R600_Reg32:$dst),
   (ins i32imm:$src0),
@@ -1378,17 +1378,6 @@ def CLAMP_R600 :  CLAMP <R600_Reg32>;
 def FABS_R600 : FABS<R600_Reg32>;
 def FNEG_R600 : FNEG<R600_Reg32>;
 
-let usesCustomInserter = 1, mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
-
-def MASK_WRITE : AMDGPUShaderInst <
-    (outs),
-    (ins R600_Reg32:$src),
-    "MASK_WRITE $src",
-    []
->;
-
-} // End usesCustomInserter = 1, mayLoad = 0, mayStore = 0, hasSideEffects = 0
-
 //===---------------------------------------------------------------------===//
 // Return instruction
 //===---------------------------------------------------------------------===//
@@ -1411,12 +1400,12 @@ def : Pat <
 // KIL Patterns
 def KILP : Pat <
   (int_AMDGPU_kilp),
-  (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO), 0))
+  (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
 >;
 
 def KIL : Pat <
   (int_AMDGPU_kill R600_Reg32:$src0),
-  (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0), 0))
+  (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
 >;
 
 // SGT Reverse args