diff options
author | Tom Stellard <thomas.stellard@amd.com> | 2013-11-05 23:32:06 -0500 |
---|---|---|
committer | Tom Stellard <thomas.stellard@amd.com> | 2014-01-31 18:06:44 -0500 |
commit | 1a41fe670b8cc455205d99e072e4c6983009d6e1 (patch) | |
tree | cc53d8406fa58209ac44e864bdd154b6973990d6 | |
parent | 80dd6af76f600034de4b737ea554ac931e1bda39 (diff) |
R600/SI: Custom lower i64 ISD::SELECT
-rw-r--r-- | lib/Target/R600/SIISelLowering.cpp | 27 | ||||
-rw-r--r-- | lib/Target/R600/SIISelLowering.h | 1 | ||||
-rw-r--r-- | test/CodeGen/R600/select64.ll | 12 |
3 files changed, 40 insertions, 0 deletions
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index 4696fdaf219..0a22d16ee1f 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -105,6 +105,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : setOperationAction(ISD::STORE, MVT::v2i32, Custom); setOperationAction(ISD::STORE, MVT::v4i32, Custom); + setOperationAction(ISD::SELECT, MVT::i64, Custom); setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); @@ -491,6 +492,7 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { } } + case ISD::SELECT: return LowerSELECT(Op, DAG); case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); case ISD::STORE: return LowerSTORE(Op, DAG); @@ -782,6 +784,31 @@ SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode, Op.getOperand(4)); } +SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { + if (Op.getValueType() != MVT::i64) + return SDValue(); + + SDLoc DL(Op); + SDValue Cond = Op.getOperand(0); + SDValue LHS = Op.getOperand(1); + SDValue RHS = Op.getOperand(2); + + SDValue Zero = DAG.getConstant(0, MVT::i32); + SDValue One = DAG.getConstant(1, MVT::i32); + + SDValue Lo0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, Zero); + SDValue Lo1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, Zero); + + SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1); + + SDValue Hi0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, One); + SDValue Hi1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, One); + + SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1); + + return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); +} + SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { SDValue LHS = Op.getOperand(0); SDValue RHS = Op.getOperand(1); diff --git a/lib/Target/R600/SIISelLowering.h b/lib/Target/R600/SIISelLowering.h index 9933eced901..c9a43e6c04f 100644 --- a/lib/Target/R600/SIISelLowering.h +++ b/lib/Target/R600/SIISelLowering.h @@ -26,6 +26,7 @@ class SITargetLowering : public AMDGPUTargetLowering { SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op, SelectionDAG &DAG) const; SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; diff --git a/test/CodeGen/R600/select64.ll b/test/CodeGen/R600/select64.ll new file mode 100644 index 00000000000..2b905a3035c --- /dev/null +++ b/test/CodeGen/R600/select64.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s + +; CHECK-LABEL: @select0 +; CHECK: V_CNDMASK +; CHECK: V_CNDMASK +define void @select0(i64 addrspace(1)* %out, i32 %cond, i64 %in) { +entry: + %0 = icmp ugt i32 %cond, 5 + %1 = select i1 %0, i64 0, i64 %in + store i64 %1, i64 addrspace(1)* %out + ret void +} |