diff options
author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-01-28 18:14:21 +0000 |
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committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-01-28 18:14:21 +0000 |
commit | 106b79744b185969faf8a74c6bd7cad35e6f11bd (patch) | |
tree | 4c15347510f68dd40e18caff39499634243557a1 | |
parent | bb6f2367296bf6e78049ff32e7fa4f7c96d80a47 (diff) |
[X86] Add extra rules for combining vselect dag nodes into movsd.
This improves the fix committed at revision 199683 adding the
following new target specific combine rules:
1) fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
(v4i32 (bitcast (movsd (v2i64 (bitcast A)), (v2i64 (bitcast B))) ))
2) fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
(v4f32 (bitcast (movsd (v2f64 (bitcast A)), (v2f64 (bitcast B))) ))
3) fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
(v4i32 (bitcast (movsd (v2i64 (bitcast B)), (v2i64 (bitcast A))) ))
4) fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
(v4f32 (bitcast (movsd (v2i64 (bitcast B)), (v2i64 (bitcast A))) ))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200324 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 40 | ||||
-rw-r--r-- | test/CodeGen/X86/sse41-blend.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/X86/vselect-2.ll | 33 |
3 files changed, 75 insertions, 2 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index f3ec8f9ac38..e292cab0262 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -17324,6 +17324,46 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG); return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG); } + + if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) { + // fold (v4i32: vselect <0,0,-1,-1>, A, B) -> + // (v4i32 (bitcast (movsd (v2i64 (bitcast A)), + // (v2i64 (bitcast B))))) + // + // fold (v4f32: vselect <0,0,-1,-1>, A, B) -> + // (v4f32 (bitcast (movsd (v2f64 (bitcast A)), + // (v2f64 (bitcast B))))) + // + // fold (v4i32: vselect <-1,-1,0,0>, A, B) -> + // (v4i32 (bitcast (movsd (v2i64 (bitcast B)), + // (v2i64 (bitcast A))))) + // + // fold (v4f32: vselect <-1,-1,0,0>, A, B) -> + // (v4f32 (bitcast (movsd (v2f64 (bitcast B)), + // (v2f64 (bitcast A))))) + + CanFold = (isZero(Cond.getOperand(0)) && + isZero(Cond.getOperand(1)) && + isAllOnes(Cond.getOperand(2)) && + isAllOnes(Cond.getOperand(3))); + + if (!CanFold && isAllOnes(Cond.getOperand(0)) && + isAllOnes(Cond.getOperand(1)) && + isZero(Cond.getOperand(2)) && + isZero(Cond.getOperand(3))) { + CanFold = true; + std::swap(LHS, RHS); + } + + if (CanFold) { + EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64; + SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS); + SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS); + SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA, + NewB, DAG); + return DAG.getNode(ISD::BITCAST, DL, VT, Select); + } + } } } diff --git a/test/CodeGen/X86/sse41-blend.ll b/test/CodeGen/X86/sse41-blend.ll index 597852c3690..4681fde7548 100644 --- a/test/CodeGen/X86/sse41-blend.ll +++ b/test/CodeGen/X86/sse41-blend.ll @@ -13,7 +13,7 @@ define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) { ;CHECK: blendvps ;CHECK: ret define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) { - %vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i8> %v1, <4 x i8> %v2 + %vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i8> %v1, <4 x i8> %v2 ret <4 x i8> %vsel } @@ -30,7 +30,7 @@ define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) { ;CHECK: blendvps ;CHECK: ret define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) { - %vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i32> %v1, <4 x i32> %v2 + %vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i32> %v1, <4 x i32> %v2 ret <4 x i32> %vsel } diff --git a/test/CodeGen/X86/vselect-2.ll b/test/CodeGen/X86/vselect-2.ll new file mode 100644 index 00000000000..50da32c67a3 --- /dev/null +++ b/test/CodeGen/X86/vselect-2.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=sse2 | FileCheck %s + +define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) { + %select = select <4 x i1><i1 true, i1 true, i1 false, i1 false>, <4 x i32> %A, <4 x i32> %B + ret <4 x i32> %select +} +; CHECK-LABEL: test1 +; CHECK: movsd +; CHECK: ret + +define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) { + %select = select <4 x i1><i1 false, i1 false, i1 true, i1 true>, <4 x i32> %A, <4 x i32> %B + ret <4 x i32> %select +} +; CHECK-LABEL: test2 +; CHECK: movsd +; CHECK-NEXT: ret + +define <4 x float> @test3(<4 x float> %A, <4 x float> %B) { + %select = select <4 x i1><i1 true, i1 true, i1 false, i1 false>, <4 x float> %A, <4 x float> %B + ret <4 x float> %select +} +; CHECK-LABEL: test3 +; CHECK: movsd +; CHECK: ret + +define <4 x float> @test4(<4 x float> %A, <4 x float> %B) { + %select = select <4 x i1><i1 false, i1 false, i1 true, i1 true>, <4 x float> %A, <4 x float> %B + ret <4 x float> %select +} +; CHECK-LABEL: test4 +; CHECK: movsd +; CHECK-NEXT: ret |