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authorTom Stellard <thomas.stellard@amd.com>2012-10-16 14:16:20 +0000
committerTom Stellard <thomas.stellard@amd.com>2012-10-17 19:20:27 +0000
commitfbadea4f5104ea7da8eedf7d134ec513ba94f4e9 (patch)
treee1caf044ef5b6f2bfdc90215abea1b0bc809021a
parent6400261747b55265c141be0b290f043c2826da09 (diff)
R600: Emit CONTINUE instructions correctly
The finalizer in mesa was incorrectly handling conditional continue instructions and the backend wasn't generating code for the unconditional version at all. This patch enables code generation for the unconditional continue and disables it for conditional continue.
-rw-r--r--lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp5
1 files changed, 2 insertions, 3 deletions
diff --git a/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
index f5e9af19179..dd2a511fa8a 100644
--- a/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -540,8 +540,7 @@ void R600MCCodeEmitter::EmitFCInstr(const MCInst &MI, raw_ostream &OS) const {
case AMDGPU::BREAK_LOGICALZ_i32:
instr = FC_BREAK_Z_INT;
break;
- case AMDGPU::CONTINUE_LOGICALNZ_f32:
- case AMDGPU::CONTINUE_LOGICALNZ_i32:
+ case AMDGPU::CONTINUE:
instr = FC_CONTINUE;
break;
case AMDGPU::IF_LOGICALNZ_f32:
@@ -633,7 +632,7 @@ bool R600MCCodeEmitter::isFCOp(unsigned opcode) const {
case AMDGPU::BREAK_LOGICALNZ_i32:
case AMDGPU::BREAK_LOGICALZ_i32:
case AMDGPU::BREAK_LOGICALNZ_f32:
- case AMDGPU::CONTINUE_LOGICALNZ_f32:
+ case AMDGPU::CONTINUE:
case AMDGPU::IF_LOGICALNZ_i32:
case AMDGPU::IF_LOGICALZ_f32:
case AMDGPU::ELSE: