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authortstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-10-03 13:39:40 +0000
committertstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-10-03 13:39:40 +0000
commitf7999358517c2da8472808d80717a606263e2a9a (patch)
tree277ba7fdc3f0a97475b690984d3a5c1c26d1486f
parenta12e30f4b221d7fce1e2364ad04cafdc45cf3dc1 (diff)
SI: Add sanity test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165111 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--test/CodeGen/SI/sanity.ll37
1 files changed, 37 insertions, 0 deletions
diff --git a/test/CodeGen/SI/sanity.ll b/test/CodeGen/SI/sanity.ll
new file mode 100644
index 00000000000..62cdcf5eca2
--- /dev/null
+++ b/test/CodeGen/SI/sanity.ll
@@ -0,0 +1,37 @@
+;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+
+; CHECK: S_ENDPGM
+
+define void @main() {
+main_body:
+ call void @llvm.AMDGPU.shader.type(i32 1)
+ %0 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*)
+ %1 = getelementptr <4 x i32> addrspace(2)* %0, i32 0
+ %2 = load <4 x i32> addrspace(2)* %1
+ %3 = call i32 @llvm.SI.vs.load.buffer.index()
+ %4 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %2, i32 0, i32 %3)
+ %5 = extractelement <4 x float> %4, i32 0
+ %6 = extractelement <4 x float> %4, i32 1
+ %7 = extractelement <4 x float> %4, i32 2
+ %8 = extractelement <4 x float> %4, i32 3
+ %9 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*)
+ %10 = getelementptr <4 x i32> addrspace(2)* %9, i32 1
+ %11 = load <4 x i32> addrspace(2)* %10
+ %12 = call i32 @llvm.SI.vs.load.buffer.index()
+ %13 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %11, i32 0, i32 %12)
+ %14 = extractelement <4 x float> %13, i32 0
+ %15 = extractelement <4 x float> %13, i32 1
+ %16 = extractelement <4 x float> %13, i32 2
+ %17 = extractelement <4 x float> %13, i32 3
+ call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %14, float %15, float %16, float %17)
+ call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %5, float %6, float %7, float %8)
+ ret void
+}
+
+declare void @llvm.AMDGPU.shader.type(i32)
+
+declare i32 @llvm.SI.vs.load.buffer.index() readnone
+
+declare <4 x float> @llvm.SI.vs.load.input(<4 x i32>, i32, i32)
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)