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authortstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-10-15 20:53:45 +0000
committertstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-10-15 20:53:45 +0000
commitdeb888ce53c17afd33f52433e49ba21b62ddba1d (patch)
tree62107f5bbda2c3c2e607385eac333cb62c271fca
parent20439c985b27f6151d8c4dad45090e7cda20dc7a (diff)
R600: use floor intrinsic instead of llvm.AMDIL.floor
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165970 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/AMDGPU/AMDGPUISelLowering.cpp1
-rw-r--r--lib/Target/AMDGPU/AMDGPUIntrinsics.td1
-rw-r--r--lib/Target/AMDGPU/R600Instructions.td2
-rw-r--r--lib/Target/AMDGPU/SIInstructions.td2
-rw-r--r--test/CodeGen/R600/floor.ll (renamed from test/CodeGen/R600/llvm.AMDGPU.floor.ll)4
5 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 14477547aff..4f5749f6342 100644
--- a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -37,6 +37,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
setOperationAction(ISD::FPOW, MVT::f32, Legal);
setOperationAction(ISD::FLOG2, MVT::f32, Legal);
setOperationAction(ISD::FABS, MVT::f32, Legal);
+ setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
setOperationAction(ISD::FRINT, MVT::f32, Legal);
setOperationAction(ISD::UDIV, MVT::i32, Expand);
diff --git a/lib/Target/AMDGPU/AMDGPUIntrinsics.td b/lib/Target/AMDGPU/AMDGPUIntrinsics.td
index c5a7bebb745..cbda5bd8361 100644
--- a/lib/Target/AMDGPU/AMDGPUIntrinsics.td
+++ b/lib/Target/AMDGPU/AMDGPUIntrinsics.td
@@ -23,7 +23,6 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
def int_AMDGPU_cndlt : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
def int_AMDGPU_div : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
def int_AMDGPU_dp4 : Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
- def int_AMDGPU_floor : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>;
def int_AMDGPU_kilp : Intrinsic<[], [], []>;
def int_AMDGPU_lrp : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td
index 40e83e8e327..4ce256d1298 100644
--- a/lib/Target/AMDGPU/R600Instructions.td
+++ b/lib/Target/AMDGPU/R600Instructions.td
@@ -405,7 +405,7 @@ def RNDNE : R600_1OP <
def FLOOR : R600_1OP <
0x14, "FLOOR",
- [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
+ [(set R600_Reg32:$dst, (ffloor R600_Reg32:$src))]
>;
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td
index eb282401497..fef8f5f27d3 100644
--- a/lib/Target/AMDGPU/SIInstructions.td
+++ b/lib/Target/AMDGPU/SIInstructions.td
@@ -573,7 +573,7 @@ defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32",
[(set VReg_32:$dst, (frint AllReg_32:$src0))]
>;
defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32",
- [(set VReg_32:$dst, (int_AMDGPU_floor AllReg_32:$src0))]
+ [(set VReg_32:$dst, (ffloor AllReg_32:$src0))]
>;
defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32",
[(set VReg_32:$dst, (fexp2 AllReg_32:$src0))]
diff --git a/test/CodeGen/R600/llvm.AMDGPU.floor.ll b/test/CodeGen/R600/floor.ll
index a96419dde26..845330f2841 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.floor.ll
+++ b/test/CodeGen/R600/floor.ll
@@ -4,7 +4,7 @@
define void @test() {
%r0 = call float @llvm.R600.load.input(i32 0)
- %r1 = call float @llvm.AMDGPU.floor( float %r0)
+ %r1 = call float @floor(float %r0)
call void @llvm.AMDGPU.store.output(float %r1, i32 0)
ret void
}
@@ -13,4 +13,4 @@ declare float @llvm.R600.load.input(i32) readnone
declare void @llvm.AMDGPU.store.output(float, i32)
-declare float @llvm.AMDGPU.floor(float ) readnone
+declare float @floor(float) readonly