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authortstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-10-03 20:49:31 +0000
committertstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-10-03 20:49:31 +0000
commitd8d7d641d60398f44ff77b9f299df7e016fba7f9 (patch)
treeb43aeefb954fc7b956fc6540ad8ee35934887165
parent26441db6da16704ad28318a5282e634608e01689 (diff)
R600: Handle more vector arithmetic instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165154 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/AMDGPU/R600ISelLowering.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp
index c9a688965ec..dc3fc949d10 100644
--- a/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -36,6 +36,14 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
setOperationAction(ISD::FADD, MVT::v4f32, Expand);
setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
+ setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
+ setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
+
+ setOperationAction(ISD::ADD, MVT::v4i32, Expand);
+ setOperationAction(ISD::AND, MVT::v4i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
+ setOperationAction(ISD::UREM, MVT::v4i32, Expand);
+ setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
setOperationAction(ISD::BR_CC, MVT::i32, Custom);
setOperationAction(ISD::BR_CC, MVT::f32, Custom);