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authortstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-10-02 14:15:43 +0000
committertstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-10-02 14:15:43 +0000
commit3cfa231f802b9ea294c847ec893964a01fc601d6 (patch)
treee92e0d913f1efe1d5f3a34418c19b8b06d64f2f6
parent1c9dfadec14f5113e84f105ce0a4a1238b116965 (diff)
R600: Fix instruction encoding for r600 family GPUs
Tested-by: Michel Dänzer <michel.daenzer@amd.com> https://bugs.freedesktop.org/show_bug.cgi?id=55217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165012 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp4
-rw-r--r--lib/Target/AMDGPU/R600Defines.h13
-rw-r--r--lib/Target/AMDGPU/R600InstrInfo.h13
3 files changed, 15 insertions, 15 deletions
diff --git a/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
index 274400aa34a..0ef0a9c2ad7 100644
--- a/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -216,8 +216,8 @@ void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI,
//older alu have different encoding for instructions with one or two src
//parameters.
- if (STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst &&
- MI.getNumOperands() < 4) {
+ if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
+ !(MCDesc.TSFlags & R600_InstFlag::OP3)) {
uint64_t ISAOpCode = InstWord01 & (0x3FFULL << 39);
InstWord01 &= ~(0x3FFULL << 39);
InstWord01 |= ISAOpCode << 1;
diff --git a/lib/Target/AMDGPU/R600Defines.h b/lib/Target/AMDGPU/R600Defines.h
index 4db199a5539..20c357cc15f 100644
--- a/lib/Target/AMDGPU/R600Defines.h
+++ b/lib/Target/AMDGPU/R600Defines.h
@@ -20,3 +20,16 @@
// Helper for finding getting the operand index for the instruction flags
// operand.
#define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
+
+namespace R600_InstFlag {
+ enum TIF {
+ TRANS_ONLY = (1 << 0),
+ TEX = (1 << 1),
+ REDUCTION = (1 << 2),
+ FC = (1 << 3),
+ TRIG = (1 << 4),
+ OP3 = (1 << 5),
+ VECTOR = (1 << 6)
+ //FlagOperand bits 7, 8
+ };
+}
diff --git a/lib/Target/AMDGPU/R600InstrInfo.h b/lib/Target/AMDGPU/R600InstrInfo.h
index 3a9aaeb4619..1c010756768 100644
--- a/lib/Target/AMDGPU/R600InstrInfo.h
+++ b/lib/Target/AMDGPU/R600InstrInfo.h
@@ -128,17 +128,4 @@ namespace llvm {
} // End llvm namespace
-namespace R600_InstFlag {
- enum TIF {
- TRANS_ONLY = (1 << 0),
- TEX = (1 << 1),
- REDUCTION = (1 << 2),
- FC = (1 << 3),
- TRIG = (1 << 4),
- OP3 = (1 << 5),
- VECTOR = (1 << 6)
- //FlagOperand bits 7, 8
- };
-}
-
#endif // R600INSTRINFO_H_