summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authortstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-10-15 20:53:43 +0000
committertstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-10-15 20:53:43 +0000
commit20439c985b27f6151d8c4dad45090e7cda20dc7a (patch)
treeeb2e7e4ed3d48db0d77865989003480f73f63ac2
parent06e57ff43ed5fce6bb3676bcd705e13ef5620cbe (diff)
R600: use llvm fabs intrinsic
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165969 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/AMDGPU/AMDGPUISelLowering.cpp3
-rw-r--r--lib/Target/AMDGPU/AMDILIntrinsics.td1
-rw-r--r--test/CodeGen/R600/fabs.ll (renamed from test/CodeGen/R600/llvm.AMDIL.fabs..ll)4
3 files changed, 3 insertions, 5 deletions
diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index f44e3d36050..14477547aff 100644
--- a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -36,6 +36,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
setOperationAction(ISD::FEXP2, MVT::f32, Legal);
setOperationAction(ISD::FPOW, MVT::f32, Legal);
setOperationAction(ISD::FLOG2, MVT::f32, Legal);
+ setOperationAction(ISD::FABS, MVT::f32, Legal);
setOperationAction(ISD::FRINT, MVT::f32, Legal);
setOperationAction(ISD::UDIV, MVT::i32, Expand);
@@ -110,8 +111,6 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return LowerIntrinsicIABS(Op, DAG);
case AMDGPUIntrinsic::AMDIL_exp:
return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
- case AMDGPUIntrinsic::AMDIL_fabs:
- return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
case AMDGPUIntrinsic::AMDGPU_lrp:
return LowerIntrinsicLRP(Op, DAG);
case AMDGPUIntrinsic::AMDIL_fraction:
diff --git a/lib/Target/AMDGPU/AMDILIntrinsics.td b/lib/Target/AMDGPU/AMDILIntrinsics.td
index 4de57674272..213c8bbfbb7 100644
--- a/lib/Target/AMDGPU/AMDILIntrinsics.td
+++ b/lib/Target/AMDGPU/AMDILIntrinsics.td
@@ -66,7 +66,6 @@ let TargetPrefix = "AMDIL", isTarget = 1 in {
}
let TargetPrefix = "AMDIL", isTarget = 1 in {
- def int_AMDIL_fabs : GCCBuiltin<"__amdil_fabs">, UnaryIntFloat;
def int_AMDIL_abs : GCCBuiltin<"__amdil_abs">, UnaryIntInt;
def int_AMDIL_bit_extract_i32 : GCCBuiltin<"__amdil_ibit_extract">,
diff --git a/test/CodeGen/R600/llvm.AMDIL.fabs..ll b/test/CodeGen/R600/fabs.ll
index a059d733f94..3911a70086d 100644
--- a/test/CodeGen/R600/llvm.AMDIL.fabs..ll
+++ b/test/CodeGen/R600/fabs.ll
@@ -4,7 +4,7 @@
define void @test() {
%r0 = call float @llvm.R600.load.input(i32 0)
- %r1 = call float @llvm.AMDIL.fabs.( float %r0)
+ %r1 = call float @fabs( float %r0)
call void @llvm.AMDGPU.store.output(float %r1, i32 0)
ret void
}
@@ -13,4 +13,4 @@ declare float @llvm.R600.load.input(i32) readnone
declare void @llvm.AMDGPU.store.output(float, i32)
-declare float @llvm.AMDIL.fabs.(float ) readnone
+declare float @fabs(float ) readnone