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authortstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-09-25 13:59:13 +0000
committertstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-09-25 13:59:13 +0000
commit18e0b9e13783459ef7ad04180cc099315122fbc1 (patch)
treec5f7a47cd1ba984c19583c5b0ca90555e3050daf
parent702e6564a2eb45a6cf8dd2ed9e58cbc57ebd3a17 (diff)
AMDGPU: Fix register encoding
The register encodings weren't being defined correctly in the .td files, so they were all encoded as 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164602 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp8
-rw-r--r--lib/Target/AMDGPU/R600RegisterInfo.td6
-rw-r--r--lib/Target/AMDGPU/SIRegisterInfo.td4
3 files changed, 6 insertions, 12 deletions
diff --git a/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
index 8dfb095d548..274400aa34a 100644
--- a/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -623,13 +623,7 @@ unsigned R600MCCodeEmitter::getHWRegChan(unsigned reg) const {
}
}
unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
- unsigned HWReg;
-
- HWReg = MRI.getEncodingValue(RegNo);
- if (AMDGPUMCRegisterClasses[AMDGPU::R600_CReg32RegClassID].contains(RegNo)) {
- HWReg += 512;
- }
- return HWReg;
+ return MRI.getEncodingValue(RegNo);
}
uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
diff --git a/lib/Target/AMDGPU/R600RegisterInfo.td b/lib/Target/AMDGPU/R600RegisterInfo.td
index 37345c603e2..21269535bc2 100644
--- a/lib/Target/AMDGPU/R600RegisterInfo.td
+++ b/lib/Target/AMDGPU/R600RegisterInfo.td
@@ -14,11 +14,11 @@ class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
foreach Index = 0-127 in {
foreach Chan = [ "X", "Y", "Z", "W" ] in {
// 32-bit Temporary Registers
- def T#Index#_#Chan : R600Reg <"T"#Index#"."#Chan, !cast<bits<16>>(Index)>;
+ def T#Index#_#Chan : R600Reg <"T"#Index#"."#Chan, Index>;
// 32-bit Constant Registers (There are more than 128, this the number
// that is currently supported.
- def C#Index#_#Chan : R600Reg <"C"#Index#"."#Chan, !cast<bits<16>>(Index)>;
+ def C#Index#_#Chan : R600Reg <"C"#Index#"."#Chan, Index>;
}
// 128-bit Temporary Registers
def T#Index#_XYZW : R600Reg_128 <"T"#Index#".XYZW",
@@ -26,7 +26,7 @@ foreach Index = 0-127 in {
!cast<Register>("T"#Index#"_Y"),
!cast<Register>("T"#Index#"_Z"),
!cast<Register>("T"#Index#"_W")],
- !cast<bits<16>>(Index)>;
+ Index>;
}
// Special Registers
diff --git a/lib/Target/AMDGPU/SIRegisterInfo.td b/lib/Target/AMDGPU/SIRegisterInfo.td
index d99d0176bc4..07850242b7f 100644
--- a/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -66,7 +66,7 @@ def POS_FIXED_PT : SIReg <"POS_FIXED_PT">;
// SGPR 32-bit registers
foreach Index = 0-103 in {
- def SGPR#Index : SGPR_32 <!cast<bits<16>>(Index), "SGPR"#Index>;
+ def SGPR#Index : SGPR_32 <Index, "SGPR"#Index>;
}
def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
@@ -97,7 +97,7 @@ def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
// VGPR 32-bit registers
foreach Index = 0-255 in {
- def VGPR#Index : VGPR_32 <!cast<bits<16>>(Index), "VGPR"#Index>;
+ def VGPR#Index : VGPR_32 <Index, "VGPR"#Index>;
}
def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,