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authorTom Stellard <thomas.stellard@amd.com>2012-10-17 15:01:47 +0000
committerTom Stellard <thomas.stellard@amd.com>2012-10-17 19:20:28 +0000
commit173d029677d04c0cf6676030574e9d757d906e9a (patch)
tree9bdf5441221815c1e5c02302ff3de383be2554ee
parent0d53003b566b715313206e4a1562191447c11fe8 (diff)
R600: Use native operands for R600_2OP instructions
-rw-r--r--lib/Target/AMDGPU/R600ISelLowering.cpp7
-rw-r--r--lib/Target/AMDGPU/R600InstrInfo.cpp28
-rw-r--r--lib/Target/AMDGPU/R600InstrInfo.h3
-rw-r--r--lib/Target/AMDGPU/R600Instructions.td164
4 files changed, 79 insertions, 123 deletions
diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp
index f233c044b98..4467c6cdbc0 100644
--- a/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -152,10 +152,9 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
// the LSHR_eg instruction as an inline literal, but I tried doing it
// this way and it didn't produce the correct results.
TII->buildMovImm(*BB, I, ShiftValue, 2);
- BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::LSHR_eg), NewAddr)
- .addOperand(MI->getOperand(1))
- .addReg(ShiftValue)
- .addReg(AMDGPU::PRED_SEL_OFF);
+ TII->buildDefaultInstruction(*BB, I, AMDGPU::LSHR_eg, NewAddr,
+ MI->getOperand(1).getReg(),
+ ShiftValue);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
.addOperand(MI->getOperand(0))
.addReg(NewAddr)
diff --git a/lib/Target/AMDGPU/R600InstrInfo.cpp b/lib/Target/AMDGPU/R600InstrInfo.cpp
index 9890bdac4b3..716c6f0c4b1 100644
--- a/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -478,9 +478,11 @@ MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MB
MachineBasicBlock::iterator I,
unsigned Opcode,
unsigned DstReg,
- unsigned Src0Reg) const
+ unsigned Src0Reg,
+ unsigned Src1Reg) const
{
- return BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode), DstReg)
+ MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
+ DstReg) // $dst
.addImm(1) // $write
.addImm(0) // $omod
.addImm(0) // $dst_rel
@@ -488,12 +490,22 @@ MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MB
.addReg(Src0Reg) // $src0
.addImm(0) // $src0_neg
.addImm(0) // $src0_rel
- .addImm(0) // $src0_abs
- //XXX: The r600g finalizer expects this to be 1, once we've moved the
- //scheduling to the backend, we can change the default to 0.
- .addImm(1) // $last
- .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
- .addImm(0); // $literal
+ .addImm(0); // $src0_abs
+
+ if (Src1Reg) {
+ MIB.addReg(Src1Reg) // $src1
+ .addImm(0) // $src1_neg
+ .addImm(0) // $src1_rel
+ .addImm(0); // $src1_abs
+ }
+
+ //XXX: The r600g finalizer expects this to be 1, once we've moved the
+ //scheduling to the backend, we can change the default to 0.
+ MIB.addImm(1) // $last
+ .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
+ .addImm(0); // $literal
+
+ return MIB;
}
MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
diff --git a/lib/Target/AMDGPU/R600InstrInfo.h b/lib/Target/AMDGPU/R600InstrInfo.h
index faef05363ae..3cf3cc16769 100644
--- a/lib/Target/AMDGPU/R600InstrInfo.h
+++ b/lib/Target/AMDGPU/R600InstrInfo.h
@@ -118,7 +118,8 @@ namespace llvm {
MachineBasicBlock::iterator I,
unsigned Opcode,
unsigned DstReg,
- unsigned Src0Reg) const;
+ unsigned Src0Reg,
+ unsigned Src1Reg = 0) const;
MachineInstr *buildMovImm(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td
index 651193fdfa6..bf11f7e6cc3 100644
--- a/lib/Target/AMDGPU/R600Instructions.td
+++ b/lib/Target/AMDGPU/R600Instructions.td
@@ -220,22 +220,41 @@ class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
[(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
>;
+// If you add our change the operands for R600_2OP instructions, you must
+// also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
+// R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
InstrItinClass itin = AnyALU> :
InstR600 <inst,
(outs R600_Reg32:$dst),
- (ins R600_Reg32:$src0, R600_Reg32:$src1,R600_Pred:$p, variable_ops),
- !strconcat(opName, " $dst, $src0, $src1"),
+ (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
+ R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs,
+ R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs,
+ LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
+ !strconcat(opName,
+ "$clamp $dst$write$dst_rel$omod, "
+ "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
+ "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
+ "$literal $pred_sel$last"),
pattern,
- itin>{
- bits<7> dst;
- bits<9> src0;
- bits<9> src1;
- let Inst{8-0} = src0;
- let Inst{21-13} = src1;
- let Inst{49-39} = inst;
- let Inst{59-53} = dst;
- }
+ itin>,
+ R600ALU_Word0,
+ R600ALU_Word1_OP2 <inst> {
+
+ let HasNativeOperands = 1;
+ let Op2 = 1;
+ let DisableEncoding = "$literal";
+
+ let Inst{31-0} = Word0;
+ let Inst{63-32} = Word1;
+}
+
+class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
+ InstrItinClass itim = AnyALU> :
+ R600_2OP <inst, opName,
+ [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
+ R600_Reg32:$src1))]
+>;
class R600_3OP <bits<11> inst, string opName, list<dag> pattern,
InstrItinClass itin = AnyALU> :
@@ -450,36 +469,16 @@ let Predicates = [isR600toCayman] in {
// Common Instructions R600, R700, Evergreen, Cayman
//===----------------------------------------------------------------------===//
-def ADD : R600_2OP <
- 0x0, "ADD",
- [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
->;
-
+def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
// Non-IEEE MUL: 0 * anything = 0
-def MUL : R600_2OP <
- 0x1, "MUL NON-IEEE",
- [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
->;
-
-def MUL_IEEE : R600_2OP <
- 0x2, "MUL_IEEE",
- [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]
->;
-
-def MAX : R600_2OP <
- 0x3, "MAX",
- [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))]
->;
-
-def MIN : R600_2OP <
- 0x4, "MIN",
- [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
->;
+def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
+def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
+def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
+def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
// For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
// so some of the instruction names don't match the asm string.
// XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
-
def SETE : R600_2OP <
0x08, "SETE",
[(set R600_Reg32:$dst,
@@ -556,50 +555,16 @@ def KILLGT : InstR600 <0x2D,
let Inst{59-53} = dst;
}
-def AND_INT : R600_2OP <
- 0x30, "AND_INT",
- [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))]
->;
-
-def OR_INT : R600_2OP <
- 0x31, "OR_INT",
- [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))]
->;
-
-def XOR_INT : R600_2OP <
- 0x32, "XOR_INT",
- [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))]
->;
-
+def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
+def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
+def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
-
-def ADD_INT : R600_2OP <
- 0x34, "ADD_INT",
- [(set R600_Reg32:$dst, (add R600_Reg32:$src0, R600_Reg32:$src1))]
->;
-
-def SUB_INT : R600_2OP <
- 0x35, "SUB_INT",
- [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))]
->;
-
-def MAX_INT : R600_2OP <
- 0x36, "MAX_INT",
- [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
-
-def MIN_INT : R600_2OP <
- 0x37, "MIN_INT",
- [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>;
-
-def MAX_UINT : R600_2OP <
- 0x38, "MAX_UINT",
- [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]
->;
-
-def MIN_UINT : R600_2OP <
- 0x39, "MIN_UINT",
- [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))]
->;
+def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
+def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
+def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
+def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
+def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUsmax>;
+def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
def SETE_INT : R600_2OP <
0x3A, "SETE_INT",
@@ -853,40 +818,19 @@ class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
inst, "LOG_IEEE", flog2
>;
-class LSHL_Common <bits<11> inst> : R600_2OP <
- inst, "LSHL $dst, $src0, $src1",
- [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))]
->;
-
-class LSHR_Common <bits<11> inst> : R600_2OP <
- inst, "LSHR $dst, $src0, $src1",
- [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))]
->;
-
-class ASHR_Common <bits<11> inst> : R600_2OP <
- inst, "ASHR $dst, $src0, $src1",
- [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))]
+class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
+class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
+class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
+class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
+ inst, "MULHI_INT", mulhs
>;
-
-class MULHI_INT_Common <bits<11> inst> : R600_2OP <
- inst, "MULHI_INT $dst, $src0, $src1",
- [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))]
->;
-
-class MULHI_UINT_Common <bits<11> inst> : R600_2OP <
- inst, "MULHI $dst, $src0, $src1",
- [(set R600_Reg32:$dst, (mulhu R600_Reg32:$src0, R600_Reg32:$src1))]
+class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
+ inst, "MULHI", mulhu
>;
-
-class MULLO_INT_Common <bits<11> inst> : R600_2OP <
- inst, "MULLO_INT $dst, $src0, $src1",
- [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))]
->;
-
-class MULLO_UINT_Common <bits<11> inst> : R600_2OP <
- inst, "MULLO_UINT $dst, $src0, $src1",
- []
+class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
+ inst, "MULLO_INT", mul
>;
+class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []>;
class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
inst, "RECIP_CLAMPED", []