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authorTom Stellard <thomas.stellard@amd.com>2012-10-16 20:38:27 +0000
committerTom Stellard <thomas.stellard@amd.com>2012-10-17 19:20:28 +0000
commit0d53003b566b715313206e4a1562191447c11fe8 (patch)
tree65dbe41823e2b6b07b6560e53e92d910cb00af22
parent0504eaa0dfb577004f1858d15e7b1694ee3b72d0 (diff)
R600: Use native operands for MOV_IMM_* instructions
-rw-r--r--lib/Target/AMDGPU/R600ISelLowering.cpp17
-rw-r--r--lib/Target/AMDGPU/R600InstrInfo.cpp11
-rw-r--r--lib/Target/AMDGPU/R600InstrInfo.h5
-rw-r--r--lib/Target/AMDGPU/R600Instructions.td32
4 files changed, 42 insertions, 23 deletions
diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp
index 4b2a5a9a5db..f233c044b98 100644
--- a/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -127,6 +127,17 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
return BB;
}
+ case AMDGPU::MOV_IMM_F32:
+ TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
+ MI->getOperand(1).getFPImm()->getValueAPF()
+ .bitcastToAPInt().getZExtValue());
+ break;
+ case AMDGPU::MOV_IMM_I32:
+ TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
+ MI->getOperand(1).getImm());
+ break;
+
+
case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
case AMDGPU::RAT_WRITE_CACHELESS_128_eg:
{
@@ -140,11 +151,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
// XXX In theory, we should be able to pass ShiftValue directly to
// the LSHR_eg instruction as an inline literal, but I tried doing it
// this way and it didn't produce the correct results.
- BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV_IMM_I32),
- ShiftValue)
- .addReg(AMDGPU::ALU_LITERAL_X)
- .addReg(AMDGPU::PRED_SEL_OFF)
- .addImm(2);
+ TII->buildMovImm(*BB, I, ShiftValue, 2);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::LSHR_eg), NewAddr)
.addOperand(MI->getOperand(1))
.addReg(ShiftValue)
diff --git a/lib/Target/AMDGPU/R600InstrInfo.cpp b/lib/Target/AMDGPU/R600InstrInfo.cpp
index 9ddea82c8cd..9890bdac4b3 100644
--- a/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -496,6 +496,17 @@ MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MB
.addImm(0); // $literal
}
+MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
+ MachineBasicBlock::iterator I,
+ unsigned DstReg,
+ uint64_t Imm) const
+{
+ MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
+ AMDGPU::ALU_LITERAL_X);
+ MovImm->getOperand(getOperandIdx(*MovImm, R600Operands::IMM)).setImm(Imm);
+ return MovImm;
+}
+
int R600InstrInfo::getOperandIdx(const MachineInstr &MI,
R600Operands::Ops Op) const
{
diff --git a/lib/Target/AMDGPU/R600InstrInfo.h b/lib/Target/AMDGPU/R600InstrInfo.h
index 33899ce6a99..faef05363ae 100644
--- a/lib/Target/AMDGPU/R600InstrInfo.h
+++ b/lib/Target/AMDGPU/R600InstrInfo.h
@@ -120,6 +120,11 @@ namespace llvm {
unsigned DstReg,
unsigned Src0Reg) const;
+ MachineInstr *buildMovImm(MachineBasicBlock &BB,
+ MachineBasicBlock::iterator I,
+ unsigned DstReg,
+ uint64_t Imm) const;
+
/// getOperandIdx - Get the index of Op in the MachineInstr. Returns -1
/// if the Instruction does not contain the specified Op.
int getOperandIdx(const MachineInstr &MI, R600Operands::Ops Op) const;
diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td
index 5eda310cfbc..651193fdfa6 100644
--- a/lib/Target/AMDGPU/R600Instructions.td
+++ b/lib/Target/AMDGPU/R600Instructions.td
@@ -516,31 +516,27 @@ def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
def MOV : R600_1OP <0x19, "MOV", []>;
-class MOV_IMM <ValueType vt, Operand immType> : InstR600 <0x19,
+let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
+
+class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
(outs R600_Reg32:$dst),
- (ins R600_Reg32:$alu_literal, R600_Pred:$p, immType:$imm),
- "MOV_IMM $dst, $imm",
- [], AnyALU
->{
- bits<7> dst;
- bits<9> alu_literal;
- bits<9> p;
- let Inst{8-0} = alu_literal;
- let Inst{21-13} = p;
- let Inst{49-39} = op_code;
- let Inst{59-53} = dst;
-}
+ (ins immType:$imm),
+ "",
+ []
+>;
+
+} // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
def : Pat <
(imm:$val),
- (MOV_IMM_I32 (i32 ALU_LITERAL_X), imm:$val)
+ (MOV_IMM_I32 imm:$val)
>;
def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
def : Pat <
(fpimm:$val),
- (MOV_IMM_F32 (i32 ALU_LITERAL_X), fpimm:$val)
+ (MOV_IMM_F32 fpimm:$val)
>;
def KILLGT : InstR600 <0x2D,
@@ -989,12 +985,12 @@ let Predicates = [isR600] in {
// cards.
class COS_PAT <InstR600 trig> : Pat<
(fcos R600_Reg32:$src),
- (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src))
+ (trig (MUL (MOV_IMM_I32 CONST.TWO_PI_INV), R600_Reg32:$src))
>;
class SIN_PAT <InstR600 trig> : Pat<
(fsin R600_Reg32:$src),
- (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src))
+ (trig (MUL (MOV_IMM_I32 CONST.TWO_PI_INV), R600_Reg32:$src))
>;
//===----------------------------------------------------------------------===//
@@ -1374,7 +1370,7 @@ def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
def : Pat <
(AMDGPUurecip R600_Reg32:$src0),
(FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
- (MOV_IMM_I32 (i32 ALU_LITERAL_X), 0x4f800000)))
+ (MOV_IMM_I32 0x4f800000)))
>;
} // End isCayman