diff options
author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2014-12-09 07:06:32 +0000 |
---|---|---|
committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2014-12-09 07:06:32 +0000 |
commit | ff3745b4ff54d627e419651339b4aad297c7c008 (patch) | |
tree | 02563c436371b465d3cab9e5939eaa3a149b3596 | |
parent | 59bf8e81f356955fbb47904b848931fb53c8afb9 (diff) |
AVX-512: Added some comments to ERI scalar intrinsics.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223761 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 7 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrAVX512.td | 16 |
2 files changed, 17 insertions, 6 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 6b4251df61a..21d1e03379f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -16790,6 +16790,13 @@ static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask, return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc); } +/// \brief Creates an SDNode for a predicated scalar operation. +/// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc). +/// The mask is comming as MVT::i8 and it should be truncated +/// to MVT::i1 while lowering masking intrinsics. +/// The main difference between ScalarMaskingNode and VectorMaskingNode is using +/// "X86select" instead of "vselect". We just can't create the "vselect" node for +/// a scalar instruction. static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask, SDValue PreservedSrc, const X86Subtarget *Subtarget, diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index 1b24163f44b..d378bd736a5 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -2,6 +2,7 @@ // EltVT). These are things like the register class for the writemask, etc. // The idea is to pass one of these as the template argument rather than the // individual arguments. +// The template is also used for scalar types, in this case numelts is 1. class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc, string suffix = ""> { RegisterClass RC = rc; @@ -23,11 +24,13 @@ class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc, // Suffix used in the instruction mnemonic. string Suffix = suffix; - int NumEltsInVT = !if (!eq (NumElts, 1), - !if (!eq (EltVT.Size, 32), 4, - !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts); - - string VTName = "v" # NumEltsInVT # EltVT; + // VTName is a string name for vector VT. For vector types it will be + // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32 + // It is a little bit complex for scalar types, where NumElts = 1. + // In this case we build v4f32 or v2f64 + string VTName = "v" # !if (!eq (NumElts, 1), + !if (!eq (EltVT.Size, 32), 4, + !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT; // The vector VT. ValueType VT = !cast<ValueType>(VTName); @@ -120,7 +123,8 @@ def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">; def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">; def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">; -// the scalar staff +// We map scalar types to the smallest (128-bit) vector type +// with the appropriate element type. This allows to use the same masking logic. def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">; def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">; |