path: root/simplex86.c

#include <stdio.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <assert.h>
#include <unistd.h>
#include <sys/types.h>
#include <sys/mman.h>

#include "simplex86.h"
#include "code-manager.h"

typedef struct inst_t inst_t;

#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1
#endif

/* Faster and more accurate op decoding:
 *
 *    There are up to 32 different op types, and
 *    arg_type_t is an enum of values whose bits
 *    indicate which of the optypes are accepted.
 *
 *    For example,
 *
 *           O_R = (1 << OP_GP8) | (1 << OP_GP16) |
 *                 (1 << OP_GP32), (1 << OP_GP64)
 *
 *    and
 *
 *           O_RM = O_R | (1 << OP_MEM)
 */
typedef enum
{
    A_CL =	(1 << OP_CL),
    A_AL =      (1 << OP_AL),
    A_AX =      (1 << OP_AX),
    A_EAX =     (1 << OP_EAX),
    A_RAX =     (1 << OP_RAX),
    A_MEM =     (1 << OP_MEM) | (1 << OP_RIP_REL),
    A_R8 =	A_CL | (1 << OP_AL) | (1 << OP_GP8) | (1 << OP_XGP8),
    A_R16 =	(1 << OP_AX) | (1 << OP_GP16) | (1 << OP_XGP16),
    A_R32 =	(1 << OP_EAX) | (1 << OP_GP32) | (1 << OP_XGP32),
    A_R64 =	(1 << OP_RAX) | (1 << OP_GP64) | (1 << OP_XGP64),
    A_RM8 =     A_R8 | A_MEM,
    A_RM16 =    A_R16 | A_MEM,
    A_RM32 =    A_R32 | A_MEM,
    A_RM64 =    A_R64 | A_MEM,
    A_R =	A_R16 | A_R32 | A_R64,
    A_RM =	A_R | A_MEM,
    A_MMX =	(1 << OP_MM),
    A_MMXM =	A_MMX | A_MEM,
    A_SSE =	(1 << OP_XMM) | (1 << OP_XXMM),
    A_SSEM =	A_SSE | A_MEM,
    A_1 =	(1 << OP_1),
    A_I8 =	A_1 | (1 << OP_I8),
    A_I16 =	A_I8 | (1 << OP_I16),
    A_I32 =	A_I16 | (1 << OP_I32),
    A_LABEL =	(1 << OP_LABEL_REF),
} arg_type_t;

typedef enum
{
    E_RM,		/* modrm, [sib], REX.W is allowed */
    E_MR,               /* modrm, [sib], REX.W is allowed */
    E_RMI,		/* modrm/d, imm */
    E_RMI2,		/* two-operand modrm, immediate (size determined by A_I8/A_I16/A_I32 */
    E_OPP,		/* opcode + reg */
    E_OPPI,             /* opcode + reg, immediate (size determined by A_I8/A_I16/A_I32 */
    E_OPPI64,		/* opcode + reg, imm64 */
    E_OP,		/* opcode only */
    E_OPI,              /* opcode, imm */
    E_JCC,		/* conditional jump */
    E_JMP,		/* jump to label */
    E_CALL,		/* call label */
    E_RM1,		/* modrm/d, allow REX.W */
    E_V0F38_2,		/* two-operand RM using VEX3 */
    E_V0F38_3,		/* three-operand RM using VEX3 */
    E_V0F3AI_4,		/* four-operand RM using VEX3, imm8 */
    E_V0F_3,		/* three-operand RM using VEX2 or VEX3 */
    E_ALIGN,		/* align */
    E_LABEL,		/* label */
    E_D8,		/* Directly emit values */
    E_D4,
    E_D2,
    E_D1
} encoding_type_t;

struct inst_t
{
    char		name[12];
    int			n_operands;
    arg_type_t		ops[4];
    encoding_type_t	encoding;
    uint32_t		opcode;
    int			modrm_op;
    int			mandatory_prefix;
    int                 disallow_rex_w;
};

static const inst_t instructions[] =
{
    /* Pseudo-instructions */
    { "label",	1, { A_LABEL },			E_LABEL			},
    { "dq",	2, { A_I32, A_I32 },		E_D8,			},
    { "dd",	1, { A_I32 },			E_D4,			},
    { "dw",	1, { A_I16 },			E_D2,			},
    { "db",	1, { A_I8 },			E_D1,			},
    { "align",	1, { A_I8 },			E_ALIGN,		},

    /* Instructions */
    { "pushf",	0, { },				E_OP,  0x9c		},
    { "popf",   0, { },				E_OP,  0x9d		},

    { "cpuid",	0, { },				E_OP,  0x0fa2		},
    { "xgetbv", 0, { },				E_OP,  0x0f01d0		},

    { "nop",	0, { },				E_OP,  0x90		},
    { "ret",	0, { },				E_OP,  0xc3		},

    { "push",	1, { A_R },			E_OPP, 0x50,		},
    { "push",	1, { A_RM },			E_RM1, 0xff, 6		},
    { "pop",	1, { A_R },			E_OPP, 0x58		},

    /* Move instructions */
    { "mov",    2, { A_R8, A_I8 },              E_OPPI, 0xb0             },
    { "mov",    2, { A_R16, A_I16 },            E_OPPI, 0xb8             },
    { "mov",    2, { A_R32, A_I32 },            E_OPPI, 0xb8             },
    { "movabs",	3, { A_R64, A_I32, A_I32 },	E_OPPI64, 0xb8		 },
    { "mov",	2, { A_RM16, A_I16 },		E_RMI, 0xc7, 0		 },
    { "mov",	2, { A_RM32, A_I32 },		E_RMI, 0xc7, 0		 },
    { "mov",	2, { A_RM64, A_I32 },		E_RMI, 0xc7, 0		 },
    { "mov",	2, { A_RM, A_R },		E_MR, 0x89		 },
    { "mov",	2, { A_R, A_RM },		E_RM, 0x8b		 },
    { "movq",   2, { A_MMX, A_MMXM },           E_RM, 0x0f6f, 0, 0,    1 },
    { "movq",   2, { A_MMXM, A_MMX },           E_MR, 0x0f7f, 0, 0,    1 },
    { "movq",	2, { A_SSE, A_SSEM },		E_RM, 0x0f7e, 0, 0xf3, 1 },
    { "movq",   2, { A_SSEM, A_SSE },           E_MR, 0x0fd6, 0, 0x66, 1 },
    { "movq2dq", 2, { A_SSE, A_MMX },           E_RM, 0x0fd6, 0, 0xf3, 1 },

    /* Unconditional jumps */
    { "jmp",   1, { A_LABEL },                  E_JMP                   },
    { "jmp",   1, { A_RM },                     E_RM1, 0xff, 4, 0, 1    },

    { "call",  1, { A_LABEL },                  E_CALL                  },
    { "call",  1, { A_RM },                     E_RM1, 0xff, 2, 0, 1    },

    /* Conditional jumps */
    { "ja",     1, { A_LABEL },                 E_JCC, 0x77             },
    { "jae",    1, { A_LABEL },                 E_JCC, 0x73             },
    { "jb",     1, { A_LABEL },                 E_JCC, 0x72             },
    { "jbe",    1, { A_LABEL },                 E_JCC, 0x76             },
    { "jc",     1, { A_LABEL },                 E_JCC, 0x72             },
    { "je",     1, { A_LABEL },                 E_JCC, 0x74             },
    { "jg",     1, { A_LABEL },                 E_JCC, 0x7f             },
    { "jge",    1, { A_LABEL },                 E_JCC, 0x7d             },
    { "jl",     1, { A_LABEL },                 E_JCC, 0x7c             },
    { "jle",    1, { A_LABEL },                 E_JCC, 0x7e             },
    { "jna",    1, { A_LABEL },                 E_JCC, 0x76             },
    { "jnae",   1, { A_LABEL },                 E_JCC, 0x72             },
    { "jnb",    1, { A_LABEL },                 E_JCC, 0x73             },
    { "jnbe",   1, { A_LABEL },                 E_JCC, 0x77             },
    { "jnc",    1, { A_LABEL },                 E_JCC, 0x73             },
    { "jne",    1, { A_LABEL },                 E_JCC, 0x75             },
    { "jng",    1, { A_LABEL },                 E_JCC, 0x7e             },
    { "jnge",   1, { A_LABEL },                 E_JCC, 0x7c             },
    { "jnl",    1, { A_LABEL },                 E_JCC, 0x7d             },
    { "jnle",   1, { A_LABEL },                 E_JCC, 0x7f             },
    { "jno",    1, { A_LABEL },                 E_JCC, 0x71             },
    { "jnp",    1, { A_LABEL },                 E_JCC, 0x7b             },
    { "jns",    1, { A_LABEL },                 E_JCC, 0x79             },
    { "jnz",    1, { A_LABEL },                 E_JCC, 0x75             },
    { "jo",     1, { A_LABEL },                 E_JCC, 0x70             },
    { "jp",     1, { A_LABEL },                 E_JCC, 0x7a             },
    { "jpe",    1, { A_LABEL },                 E_JCC, 0x7a             },
    { "jpo",    1, { A_LABEL },                 E_JCC, 0x7b             },
    { "js",     1, { A_LABEL },                 E_JCC, 0x78             },
    { "jz",     1, { A_LABEL },                 E_JCC, 0x74             },

    /* Multiplication */
    { "mul",    1, { A_RM8 }, E_RM1, 0xf6, 4 },
    { "mul",    1, { A_RM }, E_RM1, 0xf7, 4 },
    
    /* The string "imul" is insufficient to determine the number of
     * operands, so make up three different instruction names
     */
    { "imul1",  1, { A_RM8 },                   E_RM1, 0xf6, 5  },
    { "imul1",  1, { A_RM },                    E_RM1, 0xf7, 5  },
    { "imul2",  2, { A_R, A_RM },               E_RM, 0x0faf    },
    { "imul3",  3, { A_R, A_RM, A_I8 },         E_RMI2, 0x6B    },
    { "imul3",  3, { A_R16, A_RM16, A_I16 },    E_RMI2, 0x69    },
    { "imul3",  3, { A_R32, A_RM32, A_I32 },    E_RMI2, 0x69    },
    { "imul3",  3, { A_R64, A_RM64, A_I32 },    E_RMI2, 0x69    },

    /* SIMD instructions */
    
#define SIMD_OPS(name, opc)						      \
    { name,	2, { A_MMX, A_MMXM },	     E_RM, (0x0f00 + opc)	   }, \
    { name,	2, { A_SSE, A_SSEM },	     E_RM, (0x0f00 + opc), 0, 0x66 }, \
    { "v"name,	3, { A_SSE, A_SSE, A_SSEM }, E_V0F_3, opc                  }
    
    SIMD_OPS ("packsswb", 0x63),
    SIMD_OPS ("packssdw", 0x6b),
    SIMD_OPS ("packuswb", 0x67),
    SIMD_OPS ("pand", 0xdb),
    SIMD_OPS ("pandn", 0xdf),
    SIMD_OPS ("por", 0xeb),
    SIMD_OPS ("pxor", 0xef),
    SIMD_OPS ("pavgb", 0xe0),
    SIMD_OPS ("pavgw", 0xe3),
    SIMD_OPS ("paddb", 0xfc),
    SIMD_OPS ("paddw", 0xfd),
    SIMD_OPS ("paddd", 0xfe),
    SIMD_OPS ("paddq", 0xd4),
    SIMD_OPS ("paddsb", 0xec),
    SIMD_OPS ("paddsw", 0xed),
    SIMD_OPS ("paddusb", 0xdc),
    SIMD_OPS ("paddusw", 0xdd),
    SIMD_OPS ("pcmpeqb", 0x74),
    SIMD_OPS ("pcmpeqw", 0x75),
    SIMD_OPS ("pcmpeqd", 0x76),
    SIMD_OPS ("pcmpgtb", 0x64),
    SIMD_OPS ("pcmpgtw", 0x65),
    SIMD_OPS ("pcmpgtd", 0x66),
    SIMD_OPS ("pmaddwd", 0xf5),
    SIMD_OPS ("pmaxsw", 0xee),
    SIMD_OPS ("pmaxub", 0xde),
    SIMD_OPS ("pminsw", 0xea),
    SIMD_OPS ("pminub", 0xda),
    SIMD_OPS ("pmulhuw", 0xe4),
    SIMD_OPS ("pmulhw", 0xe5),
    SIMD_OPS ("pmullw", 0xd5),
    SIMD_OPS ("pmuludq", 0xf4),
    SIMD_OPS ("psadbw", 0xf6),
    SIMD_OPS ("psubb", 0xf8),
    SIMD_OPS ("psubw", 0xf9),
    SIMD_OPS ("psubd", 0xfa),
    SIMD_OPS ("psubq", 0xfb),
    SIMD_OPS ("psubsb", 0xe8),
    SIMD_OPS ("psubsw", 0xe9),
    SIMD_OPS ("psubusb", 0xd8),
    SIMD_OPS ("psubusw", 0xd9),
    SIMD_OPS ("punpckhbw", 0x68),
    SIMD_OPS ("punpckhwd", 0x69),
    SIMD_OPS ("punpckhdq", 0x6a),
    SIMD_OPS ("punpcklbw", 0x60),
    SIMD_OPS ("punpcklwd", 0x61),
    SIMD_OPS ("punpckldq", 0x62),

    { "pabsb",	2, { A_MMX, A_MMXM },	E_RM, 0x0f381c,		},
    { "pabsb",	2, { A_SSE, A_SSEM },	E_RM, 0x0f381c, 0, 0x66	},
    { "pabsw",  2, { A_MMX, A_MMXM },	E_RM, 0x0f381d,		},
    { "pabsw",  2, { A_SSE, A_SSEM },	E_RM, 0x0f381d, 0, 0x66 },
    { "pabsd",  2, { A_MMX, A_MMXM },	E_RM, 0x0f381e, 	},
    { "pabsd",  2, { A_SSE, A_SSEM },	E_RM, 0x0f381e, 0, 0x66 },
    { "vpabsb", 2, { A_SSE, A_SSEM },	E_V0F38_2, 0x1c		},
    { "vpabsw", 2, { A_SSE, A_SSEM },	E_V0F38_2, 0x1d		},
    { "vpabsw", 2, { A_SSE, A_SSEM },	E_V0F38_2, 0x1e		},

    { "packusdw", 2, { A_SSE, A_SSEM }, E_RM, 0x0f382b, 0, 0x66	},
    { "vpackusdw", 3, { A_SSE, A_SSE, A_SSEM }, E_V0F38_3, 0x2b },

    { "palignr", 3, { A_MMX, A_MMXM, A_I8 }, E_RMI2, 0x0f3a0f	},
    { "palignr", 3, { A_SSE, A_SSEM, A_I8 }, E_RMI2, 0x0f3a0f, 0, 0x66 },
    { "vpalignr", 4, {
	    A_SSE, A_SSE, A_SSEM, A_I8 },    E_V0F3AI_4, 0x0f	},

#define ALU_OPS(name, opc)                                              \
    { name,     2, { A_RM8, A_R8 },     E_RM, (opc << 3) + 0    },      \
    { name,	2, { A_RM, A_R },	E_RM, (opc << 3) + 1	},      \
    { name,	2, { A_R, A_RM },	E_RM, (opc << 3) + 3	},	\
    { name,     2, { A_AL, A_I8 },      E_OPI, (opc << 3) + 4   },	\
    { name,     2, { A_AX, A_I16 },     E_OPI, (opc << 3) + 5   },	\
    { name,     2, { A_EAX, A_I32 },    E_OPI, (opc << 3) + 5   },      \
    { name,     2, { A_RAX, A_I32 },    E_OPI, (opc << 3) + 5   },	\
    { name,	2, { A_RM8, A_I8, },	E_RMI, 0x83, opc	},	\
    { name,	2, { A_RM16, A_I16 },	E_RMI, 0x81, opc	},      \
    { name,	2, { A_RM32, A_I32 },	E_RMI, 0x81, opc	},      \
    { name,	2, { A_RM64, A_I32 },	E_RMI, 0x81, opc	}

    ALU_OPS ("add", 0),
    ALU_OPS ( "or", 1),
    ALU_OPS ("adc", 2),
    ALU_OPS ("sbb", 3),
    ALU_OPS ("and", 4),
    ALU_OPS ("sub", 5),
    ALU_OPS ("xor", 6),
    ALU_OPS ("cmp", 7),

#define SHIFT_OPS(name, opc)						\
    { name,	2, { A_RM, A_1 },	E_RM1, 0xd1, opc	},	\
    { name,	2, { A_RM, A_I8 },	E_RMI, 0xc1, opc	},	\
    { name,	2, { A_RM, A_CL },	E_RM1, 0xd3, opc	}

    SHIFT_OPS ("rol", 0),
    SHIFT_OPS ("ror", 1),
    SHIFT_OPS ("rcl", 2),
    SHIFT_OPS ("rcr", 3),
    SHIFT_OPS ("shl", 4),
    SHIFT_OPS ("shr", 5),
    SHIFT_OPS ("sal", 4),
    SHIFT_OPS ("sar", 7),
};

#define N_INST	(sizeof (instructions) / sizeof (instructions[0]))

typedef struct annotation_t annotation_t;

typedef enum
{
    LABEL, JCC, JUMP, CALL, RIP_REF, ALIGN
} annotation_type_t;

struct annotation_t
{
    annotation_type_t  type;
    size_t              offset;
    const char *        name;

    annotation_t *      label;
    bool_t              is_32;
    int			alignment;
};

struct asm_t
{
    code_manager_t *	code_manager;
    bool_t		error;

    array_t *           annotations;
    array_t *           code;
};

static void
asm_mark_error (asm_t *a, const char *error)
{
    printf ("Error: %s\n", error);
    /* FIXME: mark @a as in error and delete all state */
}

asm_t *
x86_asm_new (void)
{
    asm_t *a;

    if (!(a = malloc (sizeof *a)))
	goto oom_assembler;

    if (!(a->code_manager = code_manager_new ("pixman")))
        goto oom_code_manager;

    if (!array_create (&a->annotations, sizeof (annotation_t)))
        goto oom_annotations;

    if (!array_create (&a->code, sizeof (uint8_t)))
        goto oom_code;

    a->error = FALSE;
    return a;

oom_code:
    array_free (&a->annotations);
oom_annotations:
    code_manager_free (a->code_manager);
oom_code_manager:
    free (a);
oom_assembler:
    return NULL;
}

static bool_t
in_64_bit_mode (void)
{
#if defined(__amd64__) || defined(__x86_64__) || defined(_M_AMD64)
    return TRUE;
#else
    return FALSE;
#endif
}

static uint8_t *
emit_imm32 (uint8_t *code, int32_t imm)
{
    *code++ = (imm & 0x000000ff) >> 0;
    *code++ = (imm & 0x0000ff00) >> 8;
    *code++ = (imm & 0x00ff0000) >> 16;
    *code++ = (imm & 0xff000000) >> 24;

    return code;
}

static uint8_t *
emit_imm64 (uint8_t *code, int32_t hi, int32_t lo)
{
    code = emit_imm32 (code, lo);
    code = emit_imm32 (code, hi);

    return code;
}

static uint8_t *
emit_imm16 (uint8_t *code, int32_t imm)
{
    *code++ = (imm & 0x00ff) >> 0;
    *code++ = (imm & 0xff00) >> 8;

    return code;
}

static uint8_t *
emit_imm8 (uint8_t *code, int32_t imm)
{
    *code++ = imm & 0xff;
    return code;
}

static void
fixup_jumps (asm_t *as)
{
    int i, j, displacement;
    annotation_t *annotations;
    size_t n_annotations;
    uint8_t *code;

    /* Algorithm:
     *
     * - First match refs to labels and store a reference to the relevant
     *   instruction info.
     *
     * - Then convert jumps to 8 bit if the corresponding label is close enough.
     *   Compressing a jump may mean other jumps move into the 256 byte range,
     *   so repeat this step until no more jumps are converted.
     *
     * - Finally walk the list of references and patch in the offset.
     */
    /* FIXME: A better algorithm would be to start out with 8 bit jumps and
     * then keeps making passes doing this:
     *
     *      - expand jumps that need it
     *      - realign where necessary
     *
     * until nothing changes. It will need to know the initial alignment of the
     * final destination.
     */
    annotations = array_get_data (&as->annotations, &n_annotations);

    /* Match refs to labels */
    for (i = 0; i < n_annotations; ++i)
    {
        annotation_t *ref = &(annotations[i]);

        if (ref->type == LABEL || ref->type == ALIGN)
            continue;

        for (j = 0; j < n_annotations; ++j)
        {
            annotation_t *label = &(annotations[j]);

            if (label->type == LABEL && strcmp (ref->name, label->name) == 0)
            {
                ref->label = label;

                goto found;
            }
        }

        /* No label found */
        printf ("No label \"%s\"\n", ref->name);
        abort();

    found: ;
    }

    /* Convert jumps to 8 bit if possible and compress the code */
    do
    {
	uint8_t *c, *begin, *end;
	annotation_t *a;
        size_t n_bytes;

	displacement = 0;
	a = annotations;

        begin = array_get_data (&as->code, &n_bytes);
        end = begin + n_bytes;
	for (c = begin; c < end; ++c)
	{
	    while (a - annotations < n_annotations &&
                   a->offset == c - begin)
            {
                if ((a->type == JUMP || a->type == JCC) && a->is_32)
                {
                    annotation_t *label = a->label;

                    if (label->offset - (a->offset + 4) < 256)
                    {
                        if (a->type == JUMP)
                        {
                            *(c + 4 - 2) = 0xeb;
                            displacement += 3;
                        }
                        else
                        {
                            *(c + 4 - 2) = *(c - 1) - 0x10;
                            displacement += 4;
                        }

                        a->is_32 = FALSE;
                        a->offset += 3;
                        c += 2;
                    }
                }
		else if (a->type == ALIGN)
		{
		    displacement &= ~(a->alignment - 1);
		}

                a->offset -= displacement;
                a++;
            }

            *(c - displacement) = *c;
	}

        array_delete_tail (&as->code, displacement);
    }
    while (displacement);

    /* Patch in the offsets */
    code = array_get_data (&as->code, NULL);
    for (i = 0; i < n_annotations; ++i)
    {
	annotation_t *ref;

	ref = &annotations[i];

	if (ref->type != LABEL && ref->type != ALIGN)
	{
	    annotation_t *label = ref->label;

	    if (ref->is_32)
	    {
		int32_t rel = label->offset - (ref->offset + 4);

		emit_imm32 (code + ref->offset, rel);
	    }
	    else
	    {
		int8_t rel = label->offset - (ref->offset + 1);

		emit_imm8 (code + ref->offset, rel);
	    }
	}
    }
}

uint8_t *
x86_asm_emit (asm_t *a)
{
    uint8_t *writable, *executable;
    uint8_t *result = NULL;
    uint8_t *code;
    size_t n_bytes;

    code = array_get_data (&a->code, &n_bytes);

    if (code_manager_alloc (
	    a->code_manager, "hello", n_bytes,
	    &writable, &executable))
    {
	fixup_jumps (a);

	memcpy (writable, code, n_bytes);

	result = executable;
    }

    array_clear (&(a->annotations));
    array_clear (&(a->code));

    return result;
}

/* Code generation */
typedef enum
{
    OP_FAKE_REG	= OP_N_OP_TYPES
} fake_ops_t;

typedef struct
{
    int			regno;
    op_type_t		op_type;
} register_info_t;

static const register_info_t register_map[] =
{
    /* regnos */
    [0] =  { 0, OP_FAKE_REG },  [1]  = { 1, OP_FAKE_REG },
    [2] =  { 2, OP_FAKE_REG },  [3]  = { 3, OP_FAKE_REG },
    [4] =  { 4, OP_FAKE_REG },  [5]  = { 5, OP_FAKE_REG },
    [6] =  { 6, OP_FAKE_REG },  [7]  = { 7, OP_FAKE_REG },
    [8] =  { 8, OP_FAKE_REG },  [9]  = { 9, OP_FAKE_REG },
    [10] = { 10, OP_FAKE_REG }, [11] = { 11, OP_FAKE_REG },
    [12] = { 12, OP_FAKE_REG }, [13] = { 13, OP_FAKE_REG },
    [14] = { 14, OP_FAKE_REG }, [15] = { 15, OP_FAKE_REG },

    [NO_REG] = { NO_REG, OP_FAKE_REG },
    [RIP_REG] = { RIP_REG, OP_FAKE_REG },

    /* 8 bit registers */
    [   AL] = {  0, OP_AL },     [   CL] = {  1, OP_CL },
    [   DL] = {  2, OP_GP8 },    [   BL] = {  3, OP_GP8 },
    [   AH] = {  4, OP_GP8 },    [   CH] = {  5, OP_GP8 },
    [   DH] = {  6, OP_GP8 },    [   BH] = {  7, OP_GP8 },
    [  R8L] = {  8, OP_XGP8 },   [  R9L] = {  9, OP_XGP8 },
    [ R10L] = { 10, OP_XGP8 },   [ R11L] = { 11, OP_XGP8 },
    [ R12L] = { 12, OP_XGP8 },   [ R13L] = { 13, OP_XGP8 },
    [ R14L] = { 14, OP_XGP8 },   [ R15L] = { 15, OP_XGP8 },

    /* 16 bit registers */
    [   AX] = {  0, OP_AX },     [   CX] = {  1, OP_GP16 },
    [   DX] = {  2, OP_GP16 },   [   BX] = {  3, OP_GP16 },
    [   SP] = {  4, OP_GP16 },   [   BP] = {  5, OP_GP16 },
    [   SI] = {  6, OP_GP16 },   [   DI] = {  7, OP_GP16 },
    [  R8W] = {  8, OP_XGP16 },  [  R9W] = {  9, OP_XGP16 },
    [ R10W] = { 10, OP_XGP16 },  [ R11W] = { 11, OP_XGP16 },
    [ R12W] = { 12, OP_XGP16 },  [ R13W] = { 13, OP_XGP16 },
    [ R14W] = { 14, OP_XGP16 },  [ R15W] = { 15, OP_XGP16 },

    /* 32 bit registers */
    [  EAX] = {  0, OP_EAX },    [  ECX] = {  1, OP_GP32 },
    [  EDX] = {  2, OP_GP32 },   [  EBX] = {  3, OP_GP32 },
    [  ESP] = {  4, OP_GP32 },   [  EBP] = {  5, OP_GP32 },
    [  ESI] = {  6, OP_GP32 },   [  EDI] = {  7, OP_GP32 },
    [  R8D] = {  8, OP_XGP32 },  [  R9D] = {  9, OP_XGP32 },
    [ R10D] = { 10, OP_XGP32 },  [ R11D] = { 11, OP_XGP32 },
    [ R12D] = { 12, OP_XGP32 },  [ R13D] = { 13, OP_XGP32 },
    [ R14D] = { 14, OP_XGP32 },  [ R15D] = { 15, OP_XGP32 },

    /* 64 bit registers */
    [  RAX] = {  0, OP_RAX },    [  RCX] = {  1, OP_GP64 },
    [  RDX] = {  2, OP_GP64 },   [  RBX] = {  3, OP_GP64 },
    [  RSP] = {  4, OP_GP64 },   [  RBP] = {  5, OP_GP64 },
    [  RSI] = {  6, OP_GP64 },   [  RDI] = {  7, OP_GP64 },
    [   R8] = {  8, OP_XGP64 },  [   R9] = {  9, OP_XGP64 },
    [  R10] = { 10, OP_XGP64 },  [  R11] = { 11, OP_XGP64 },
    [  R12] = { 12, OP_XGP64 },  [  R13] = { 13, OP_XGP64 },
    [  R14] = { 14, OP_XGP64 },  [  R15] = { 15, OP_XGP64 },

    /* 64 bit mmx registers */
    [  MM0] = {  0, OP_MM },     [  MM1] = {  1, OP_MM },
    [  MM2] = {  2, OP_MM },     [  MM3] = {  3, OP_MM },
    [  MM4] = {  4, OP_MM },     [  MM5] = {  5, OP_MM },
    [  MM6] = {  6, OP_MM },     [  MM7] = {  7, OP_MM },

    /* 128 bit SSE registers */
    [ XMM0] = {  0, OP_XMM },    [ XMM1] = {  1, OP_XMM },
    [ XMM2] = {  2, OP_XMM },    [ XMM3] = {  3, OP_XMM },
    [ XMM4] = {  4, OP_XMM },    [ XMM5] = {  5, OP_XMM },
    [ XMM6] = {  6, OP_XMM },    [ XMM7] = {  7, OP_XMM },
    [ XMM8] = {  8, OP_XMM },    [ XMM9] = {  9, OP_XMM },
    [XMM10] = { 10, OP_XXMM },   [XMM11] = { 11, OP_XXMM },
    [XMM12] = { 12, OP_XXMM },   [XMM13] = { 13, OP_XXMM },
    [XMM14] = { 14, OP_XXMM },   [XMM15] = { 15, OP_XXMM },

    /* 256 bit AVX registers */
    [ YMM0] = {  0, OP_YMM },    [ YMM1] = {  1, OP_YMM },
    [ YMM2] = {  2, OP_YMM },    [ YMM3] = {  3, OP_YMM },
    [ YMM4] = {  4, OP_YMM },    [ YMM5] = {  5, OP_YMM },
    [ YMM6] = {  6, OP_YMM },    [ YMM7] = {  7, OP_YMM },
    [ YMM8] = {  8, OP_YMM },    [ YMM9] = {  9, OP_YMM },
    [YMM10] = { 10, OP_YMM },    [YMM11] = { 11, OP_YMM },
    [YMM12] = { 12, OP_YMM },    [YMM13] = { 13, OP_YMM },
    [YMM14] = { 14, OP_YMM },    [YMM15] = { 15, OP_YMM },
};

op_type_t
reg_to_op_type (reg_t reg)
{
    return register_map[reg].op_type;
}

static bool_t
is_extended (reg_t reg)
{
    /* FIXME: Rethink NO_REG */
    if (reg == NO_REG)
	return FALSE;
    return !!(register_map[reg].regno & 0x8);
}

static int
reg_to_regno (reg_t reg)
{
    /* FIXME: Rethink NO_REG */
    if (reg == NO_REG)
	return NO_REG;
    return register_map[reg].regno;
}

static uint8_t *
emit_address_byte (uint8_t *code,
		   int m,
		   int o,
		   int r,
		   uint8_t *e1,
		   uint8_t *e2)
{
    if (e1)
	*e1 = (o & 0x8) >> 3;
    if (e2)
	*e2 = (r & 0x8) >> 3;

    *code++ =
	((m & 0x03) << 6) |
	((o & 0x07) << 3) |
	((r & 0x07));

    return code;
}

static int
is_s8 (int32_t x)
{
    return x >= -128 && x < 128;
}

static int
is_rip_rel (op_t op)
{
    return GET_TYPE (op) == OP_RIP_REL;
}

static int
is_type (op_t op, uint32_t types)
{
    return (types & (1 << GET_TYPE (op))) != 0;
}

static int
is_reg (op_t op)
{
    return is_type (op, A_R8 | A_R | A_MMX | A_SSE) || (GET_TYPE (op) == OP_FAKE_REG);
}

static int
op_to_regno (op_t op)
{
    assert (is_reg (op));

    return reg_to_regno (GET_REG (op));
}

static uint8_t *
emit_reg_regm (uint8_t *code, op_t reg, op_t regm,
	       uint8_t *r, uint8_t *x, uint8_t *b,
	       const uint8_t **rip_disp, const char **label)
{
    assert (is_reg (reg));

    if (is_rip_rel (regm))
    {
	/* In 64 bit mode, this is an RIP-based address, in
	 * 32 bit mode it's an absolute address.
	 */
	code = emit_address_byte (code, 0, op_to_regno (reg), 5, r, NULL);
	code = emit_imm32 (code, 0x00000000);

	*rip_disp = code - 4;
	*label = GET_LABEL (regm);
    }
    else if (is_reg (regm))
    {
	code = emit_address_byte (
	    code, 3, op_to_regno (reg), op_to_regno (regm), r, b);
    }
    else
    {
	int base_regno = reg_to_regno (GET_BASE (regm));
	int index_regno = reg_to_regno (GET_INDEX (regm));
	int32_t disp = GET_DISP (regm);
	int regno = op_to_regno (reg);
	int ebp_regno = reg_to_regno (EBP);
	int esp_regno = reg_to_regno (ESP);
	int r13_regno = reg_to_regno (R13);
	int shift = GET_SHIFT (regm);

	if (index_regno == esp_regno)
	    index_regno = NO_REG;

	if (index_regno == NO_REG)
	{
	    if (base_regno == NO_REG && in_64_bit_mode())
	    {
		code = emit_address_byte (code, 0, regno, 4, r, NULL);
		code = emit_address_byte (code, 0, 4, 5, NULL, NULL);
		code = emit_imm32 (code, disp);
	    }
	    else if (base_regno == NO_REG || base_regno == RIP_REG)
	    {
		/* In 64 bit mode, this is an RIP-based address, in
		 * 32 bit mode it's an absolute address.
		 */
		code = emit_address_byte (code, 0, regno, 5, r, NULL);
		code = emit_imm32 (code, disp);
	    }
	    else if (base_regno == esp_regno)
	    {
		if (disp == 0)
		{
		    code = emit_address_byte (code, 0, regno, esp_regno, r, NULL);
		    code = emit_address_byte (code, 0, esp_regno, esp_regno, x, b);
		}
		else if (is_s8 (disp))
		{
		    code = emit_address_byte (code, 1, regno, esp_regno, r, NULL);
		    code = emit_address_byte (code, 0, esp_regno, esp_regno, x, b);
		    code = emit_imm8 (code, disp);
		}
		else
		{
		    code = emit_address_byte (code, 2, regno, esp_regno, r, NULL);
		    code = emit_address_byte (code, 0, esp_regno, esp_regno, x, b);
		    code = emit_imm32 (code, disp);
		}
	    }
	    else if (disp == 0 && base_regno != ebp_regno && base_regno != r13_regno)
	    {
		code = emit_address_byte (code, 0, regno, base_regno, r, b);
	    }
	    else if (is_s8 (disp))
	    {
		code = emit_address_byte (code, 1, regno, base_regno, r, b);
		code = emit_imm8 (code, disp);
	    }
	    else
	    {
		code = emit_address_byte (code, 2, regno, base_regno, r, b);
		code = emit_imm32 (code, disp);
	    }
	}
	else if (base_regno == NO_REG)
	{
	    code = emit_address_byte (code, 0, regno, 4, r, NULL);
	    code = emit_address_byte (code, shift, index_regno, 5, x, b);
	    code = emit_imm32 (code, disp);
	}
	else if (disp == 0 && base_regno != ebp_regno && base_regno != r13_regno)
	{
	    code = emit_address_byte (code, 0, regno, 4, r, NULL);
	    code = emit_address_byte (code, shift, index_regno, base_regno, x, b);
	}
	else if (is_s8 (disp))
	{
	    code = emit_address_byte (code, 1, regno, 4, r, NULL);
	    code = emit_address_byte (code, shift, index_regno, base_regno, x, b);
	    code = emit_imm8 (code, disp);
	}
	else
	{
	    code = emit_address_byte (code, 2, regno, 4, r, NULL);
	    code = emit_address_byte (code, shift, index_regno, 5, x, NULL);
	    code = emit_imm32 (code, disp);
	}
    }

    return code;
}

static uint8_t *
emit_opcode (uint8_t *c, uint32_t opc)
{
    if (opc & 0xff000000)
	*c++ = (opc & 0xff000000) >> 24;
    if (opc & 0xff0000)
	*c++ = (opc & 0xff0000) >> 16;
    if (opc & 0xff00)
	*c++ = (opc & 0xff00) >> 8;
    if (opc & 0xff)
	*c++ = (opc & 0xff) >> 0;

    return c;
}

static bool_t
is_32 (reg_t reg)
{
    /* FIXME: Rethink NO_REG */
    if (reg == NO_REG)
	return FALSE;

    return (1 << register_map[reg].op_type) & A_R32;
}

static bool_t
need_16bit_prefix (int n_ops, op_t ops[4])
{
    int i;

    for (i = 0; i < n_ops; ++i)
    {
        if (is_type (ops[i], A_R16))
            return TRUE;
    }

    return FALSE;
}

static bool_t
size_is_64_bit (int n_ops, op_t ops[4])
{
    int i;

    for (i = 0; i < n_ops; ++i)
    {
        if (is_type (ops[i], A_R64))
            return TRUE;
    }

    return FALSE;
}

static bool_t
need_address_size_override (int n_ops, op_t ops[4])
{
    int i;

    if (in_64_bit_mode ())
    {
	for (i = 0; i < n_ops; ++i)
	{
	    if (GET_TYPE (ops[i]) == OP_MEM	&&
		(is_32 (GET_BASE (ops[i])) || is_32 (GET_INDEX (ops[i]))))
	    {
		return TRUE;
	    }
	}
    }

    return FALSE;
}

static bool_t
need_rex (int n_ops, op_t ops[4], uint8_t *w)
{
    /* A REX prefix is needed when
     *
     *  (a) the size of the instruction data is 64 bits, or
     *  (b) one of the extended registers (R9-R15) is used
     */

    bool_t needed = FALSE;
    int i;

    if (size_is_64_bit (n_ops, ops))
    {
        *w = TRUE;
        needed = TRUE;
    }
    
#define SIZE_IS_64	((1 << OP_RAX) | (1 << OP_GP64) | (1 << OP_XGP64))
#define EXTENDED_REG	((1 << OP_XGP8) | (1 << OP_XGP16) |		\
			 (1 << OP_XGP32) | (1 << OP_XGP64) |		\
			 (1 << OP_XXMM))

    for (i = 0; i < n_ops; ++i)
    {
	if (is_type (ops[i], EXTENDED_REG))
	    needed = TRUE;

	if (is_type (ops[i], A_MEM))
	{
	    /* Addresses are 64 bit by default, so using a 64 bit
	     * register does not in itself require a REX prefix.
	     * (We may need to add a MEM64 op type that forces
	     * the operand size to wide. And MEM32/MEM8 types
	     * for that matter).
	     */
	    if (is_extended (GET_BASE (ops[i]))	||
		is_extended (GET_INDEX (ops[i])))
	    {
		needed = TRUE;
	    }
	}
    }

    return needed;
}

static void
add_annotation (asm_t *as, annotation_type_t type, const char *label,
		int alignment, size_t offset)
{
    annotation_t *info;

    if (!array_append (&as->annotations, 1, &info))
    {
        /* FIXME: mark eerror */
        return;
    }

    info->type = type;
    info->offset = offset;

    info->name = label;
    info->label = NULL;
    info->is_32 = TRUE;
    info->alignment = alignment;
}

#define MAKE_REX(w, r, x, b)						\
    (0x40 | ((w) << 3) | ((r) << 2) | ((x) << 1) | ((b) << 0))

#define VEX_0F	 0x01
#define VEX_0F38 0x02
#define VEX_0F3A 0x03

#define VEX_66   0x01

static uint8_t *
emit_vex3 (uint8_t *c,
	   bool_t r, bool_t x, bool_t b,
	   uint8_t mmmm, bool_t w, uint8_t vvvv, bool_t l, uint8_t pp)
{
    *c++ = 0xc4;
    *c++ = ((!r) << 7) | ((!x) << 6) | ((!b) << 5) | mmmm;
    *c++ = (w << 7) | (((~vvvv) & 0xf) << 3) | (l << 2) | pp;

    return c;
}

static uint8_t *
emit_vex2 (uint8_t *c, bool_t r, uint8_t vvvv, bool_t l, uint8_t pp)
{
    *c++ = 0xc5;
    *c++ = ((!r) << 7) | (((~vvvv) & 0xf) << 3) | (l << 2) | pp;

    return c;
}

static uint8_t *
emit_imm (uint8_t *c, arg_type_t size, int32_t immediate)
{
    if (size == A_I8)
        c = emit_imm8 (c, immediate);
    else if (size == A_I16)
        c = emit_imm16 (c, immediate);
    else if (size == A_I32)
        c = emit_imm32 (c, immediate);

    return c;
}

static void
emit (asm_t *as, const inst_t *inst, op_t ops[4])
{
    uint8_t tmp[16];
    uint8_t code[16];
    uint32_t opc;
    uint8_t *c, *d;
    uint8_t *rex = NULL;
    uint8_t w, r, x, b;
    int regno;
    bool_t is_16_bit;
    size_t offset;

    annotation_type_t ann_type;
    const uint8_t *ann_pos;
    const char *ann_name;
    int ann_alignment;

    c = code;

    ann_type = RIP_REF;
    ann_pos = NULL;
    ann_name = NULL;

    w = r = x = b = FALSE;

    if (need_address_size_override (inst->n_operands, ops))
	*c++ = 0x67;

    if ((is_16_bit = need_16bit_prefix (inst->n_operands, ops)))
        *c++ = 0x66;

    switch (inst->encoding)
    {
    case E_ALIGN:
	ann_alignment = GET_IMM (ops[0]);
	ann_type = ALIGN;
	ann_pos = c;
	ann_name = NULL;
	break;

    case E_OPP:
	regno = op_to_regno (ops[0]);
	if (regno & 0x8)
	    *c++ = MAKE_REX (0, 0, 0, 1); /* REX.B */
	opc = inst->opcode + (regno & 0x7);
	c = emit_opcode (c, opc);
	break;

    case E_OPI:
        if (size_is_64_bit (inst->n_operands, ops))
            *c++ = MAKE_REX (1, 0, 0, 0);
        *c++ = inst->opcode;
        c = emit_imm (c, inst->ops[1], GET_IMM (ops[1]));
        break;

    case E_OPPI:
        regno = op_to_regno (ops[0]);
        if (regno & 0x8)
            *c++ = MAKE_REX (0, 0, 0, 1);
        opc = inst->opcode + (regno & 0x7);
        c = emit_opcode (c, opc);
        c = emit_imm (c, inst->ops[1], GET_IMM (ops[1]));
        break;
        
    case E_OPPI64:
	regno = op_to_regno (ops[0]);
	b = !!(regno & 0x8);
	*c++ = MAKE_REX (1, 0, 0, b);
	opc = inst->opcode + (regno & 0x7);
	c = emit_opcode (c, opc);
	c = emit_imm64 (c, GET_IMM (ops[1]), GET_IMM (ops[2]));
	break;

    case E_OP:
	c = emit_opcode (c, inst->opcode);
	break;

    case E_RMI:
	if (need_rex (inst->n_operands, ops, &w))
	    rex = c++;
	c = emit_opcode (c, inst->opcode);
        c = emit_reg_regm (c, REG (inst->modrm_op), ops[0], &r, &x, &b, &ann_pos, &ann_name);
        c = emit_imm (c, inst->ops[1], GET_IMM (ops[1]));
	if (rex)
	    *rex = MAKE_REX (w, r, x, b);
        break;

    case E_RMI2:
	if (need_rex (inst->n_operands, ops, &w))
	    rex = c++;
	c = emit_opcode (c, inst->opcode);
        c = emit_reg_regm (c, ops[0], ops[1], &r, &x, &b, &ann_pos, &ann_name);
        c = emit_imm (c, inst->ops[2], GET_IMM (ops[2]));
	if (rex)
	    *rex = MAKE_REX (w, r, x, b);
	break;

    case E_RM:
    case E_MR:
	if (inst->mandatory_prefix)
	    *c++ = inst->mandatory_prefix;
	d = emit_opcode (tmp, inst->opcode);
        if (inst->encoding == E_RM)
            d = emit_reg_regm (d, ops[0], ops[1], &r, &x, &b, &ann_pos, &ann_name);
        else
            d = emit_reg_regm (d, ops[1], ops[0], &r, &x, &b, &ann_pos, &ann_name);
        w = (!inst->disallow_rex_w && size_is_64_bit (inst->n_operands, ops));
	if (w || r || x || b)
            *c++ = MAKE_REX (w, r, x, b);
        memcpy (c, tmp, d - tmp);
        if (ann_pos)
            ann_pos += (c - tmp);
        c += (d - tmp);
	break;

    case E_RM1:
	d = emit_opcode (tmp, inst->opcode);
	d = emit_reg_regm (d, REG (inst->modrm_op), ops[0], &r, &x, &b, &ann_pos, &ann_name);
        w = (!inst->disallow_rex_w && size_is_64_bit (inst->n_operands, ops));
	if (w || r || x || b)
	    *c++ = MAKE_REX (w, r, x, b);
	memcpy (c, tmp, d - tmp);
	if (ann_pos)
	    ann_pos += (c - tmp);
	c += (d - tmp);
	break;

    case E_V0F38_2:
	d = emit_reg_regm (
	    tmp, ops[0], ops[1], &r, &x, &b, &ann_pos, &ann_name);
	c = emit_vex3 (c, r, x, b, VEX_0F38, 0, 0x0, 0, VEX_66);
	c = emit_opcode (c, inst->opcode);
	memcpy (c, tmp, d - tmp);
	if (ann_pos)
	    ann_pos += (c - tmp);
	c += d - tmp;
	break;

    case E_V0F38_3:
	d = emit_reg_regm (tmp, ops[0], ops[2], &r, &x, &b, &ann_pos, &ann_name);
	c = emit_vex3 (c, r, x, b, VEX_0F38, 0, op_to_regno (ops[1]), 0, VEX_66);
	c = emit_opcode (c, inst->opcode);
	memcpy (c, tmp, d - tmp);
	if (ann_pos)
	    ann_pos += (c - tmp);
	c += d - tmp;
	break;

    case E_V0F3AI_4:
	d = emit_reg_regm (tmp, ops[0], ops[2], &r, &x, &b, &ann_pos, &ann_name);
	c = emit_vex3 (c, r, x, b, VEX_0F3A, 0, op_to_regno (ops[1]), 0, VEX_66);
	c = emit_opcode (c, inst->opcode);
	memcpy (c, tmp, d - tmp);
	if (ann_pos)
	    ann_pos += (c - tmp);
	c += d - tmp;
	c = emit_imm8 (c, GET_IMM (ops[3]));
	break;

    case E_V0F_3:
	d = emit_reg_regm (tmp, ops[0], ops[2], &r, &x, &b, &ann_pos, &ann_name);
	if (!x && !b)
	    c = emit_vex2 (c, r, op_to_regno (ops[1]), 0, VEX_66);
	else
	    c = emit_vex3 (c, r, x, b, VEX_0F, 0, op_to_regno (ops[1]), 0, VEX_66);
	c = emit_opcode (c, inst->opcode);
	memcpy (c, tmp, d - tmp);
	if (ann_pos)
	    ann_pos += (c - tmp);
	c += d - tmp;
	break;

    case E_D8:
	c = emit_imm64 (c, GET_IMM (ops[0]), GET_IMM (ops[1]));
	break;

    case E_D4:
	c = emit_imm32 (c, GET_IMM (ops[0]));
	break;

    case E_D2:
	c = emit_imm16 (c, GET_IMM (ops[0]));
	break;

    case E_D1:
	c = emit_imm8 (c, GET_IMM (ops[0]));
	break;

    case E_LABEL:
        ann_type = LABEL;
        ann_name = GET_LABEL (ops[0]);
        ann_pos = c;
	break;

    case E_JCC:
        *c++ = 0x0f;
        *c++ = inst->opcode + 0x10;

        ann_type = JCC;
        ann_name = GET_LABEL (ops[0]);
        ann_pos = c;

        c = emit_imm32 (c, 0x00000000);
        break;

    case E_JMP:
        *c++ = 0xe9;

        ann_type = JUMP;
        ann_name = GET_LABEL (ops[0]);
        ann_pos = c;

        c = emit_imm32 (c, 0x00000000);
        break;

    case E_CALL:
        *c++ = 0xe8;

        ann_type = CALL;
        ann_name = GET_LABEL (ops[0]);
        ann_pos = c;

        c = emit_imm32 (c, 0x00000000);
        break;
    }

    array_get_data (&as->code, &offset);
    
    if (ann_pos)
    {
	add_annotation (
	    as, ann_type, ann_name, ann_alignment, offset + (ann_pos - code));
    }

    printf ("offset %lx:  ", offset);
    for (d = code; d < c; ++d)
	printf ("%02x ", *d);
    printf ("\n");

    array_append (&as->code, c - code, &d);
    memcpy (d, code, c - code);
}

static bool_t
match (const inst_t *inst, op_t ops[4])
{
    int i;

    for (i = 0; i < inst->n_operands; ++i)
    {
	if (!(inst->ops[i] & (1 << GET_TYPE (ops[i]))))
	    return FALSE;
    }

    return TRUE;
}

static void
generate (asm_t *as, const char *name, const inst_t *inst, op_t ops[4])
{
    do
    {
	if (match (inst, ops))
	{
	    if (strcmp (name, inst->name) != 0)
		break;

	    emit (as, inst, ops);
	    return;
	}
    } while (++inst < instructions + N_INST);

    printf ("unknown %s\n", name);
    asm_mark_error (as, "Unknown instruction");
    abort();
}

void
x86_asm (asm_t *as, const char *name, ...)
{
    int i;
    va_list va;

    va_start (va, name);
    do
    {
	for (i = 0; i < N_INST; ++i)
	{
	    if (strcmp (instructions[i].name, name) == 0)
	    {
		const inst_t *inst = &(instructions[i]);
		op_t ops[4];

		for (i = 0; i < inst->n_operands; ++i)
		    ops[i] = va_arg (va, op_t);

		generate (as, name, inst, ops);
		break;
	    }
	}

	if (i == N_INST)
	{
            printf ("Instruction %s does not exist\n", name);
	    asm_mark_error (as, "Non-existent instruction");
	    break;
	}

	name = va_arg (va, const char *);

    } while (name != NULL);

    va_end (va);
}

int
dummy (void)
{
    return 1234;
} 

static bool_t
avx_supported (asm_t *as)
{
    uint8_t *code;
    typedef int (* func) (void);

    x86_asm (
	as,
	"push",   rcx,
	"push",   rdx,
        "mov",    eax, IMM (1),
	"cpuid",
	"and",    ecx, IMM (0x18000000),
	"cmp",    ecx, IMM (0x18000000),
	"jne",    LABEL ("not_supported"),
	/* processor supports AVX instructions and XGETBV is enabled by OS */
	"xor",    ecx, ecx,  // specify 0 for XFEATURE_ENABLED_MASK register
	"xgetbv",	      // result in EDX:EAX
	"and",    al, IMM (0x06),
	"cmp",    al, IMM (0x06),
	"jne",    LABEL ("not_supported"),
	"mov",    eax, IMM (1),
	"jmp",    LABEL ("done"),
	DEFINE_LABEL ("not_supported"),
	"mov",    eax, IMM (0),
	DEFINE_LABEL ("done"),
	"pop",    rdx,
	"pop",    rcx,
	"ret",
	NULL);

    code = x86_asm_emit (as);

    return ((func)code)();
}

int
main ()
{
    asm_t *as = x86_asm_new ();
    uint8_t *code;
    uint8_t sandbox[1024];

    printf ("AVX supported: %s\n",
	    avx_supported (as)? "yes" : "no");
    
    x86_asm (
	as,

	DEFINE_LABEL ("begin"),
        "add",          edx, ebx,
        "add",          ebx, edx,
        "add",          rax, IMM (17),
        "add",          eax, IMM (17),
        "mul",          rbx,
        "mul",          al,
        "mul",          ebp,
        "mul",          r9l,

        "imul2",        r9, r9,
        
        "imul3",        ax, r9w, IMM (17),
        "imul3",        r9d, RIP_REL ("printf"), IMM (0x7befe57),
        
        "movabs",       rbx, IMM64 (&sandbox),
	"movq",		xmm0, BASE (rbx, 127),

        "mov",          al, IMM (0),
	"mov",		r13, RIP_REL ("printf"),
	"mov",		rdi, RIP_REL ("hello"),
	"call",		r13,

        "sub",          ax, IMM (234),
        
        /* The ABI spec claims that %al is used as an "upper bound" of
         * the number of vector registers used in a vararg function.
         * However, if we don't set %al to 0 here, printf crashes.
         */
        "mov",          al, IMM (0),
        "mov",          r9l, IMM (0),
        "mov",          ah, IMM (8),
	"mov",		r13, RIP_REL ("printf"),
	"mov",		rdi, RIP_REL ("hello2"),
        "call",         r13,

        "mov",          eax, IMM(32),
        "movq",         mm7, mm2,
        "movq",         mm3, RIP_REL ("printf"),
        "movq",         INDEX (rbx, 17, rax, 4), mm2,
        "movq",         xmm9, RIP_REL ("printf"),
        "movq",         INDEX (rbx, 17, rax, 4), xmm2,
        "movq",         xmm9, xmm7,
        "movq2dq",      xmm9, mm7,
        
	"mov",		rsi, rax,
	"mov",		rdi, RIP_REL ("retval"),
	"xor",		rax, rax,
	"call",		r13,

        "xor",          al, al,
	"mov",		rdi, RIP_REL ("hello2"),
        "call",         RIP_REL("printf"),

	"add",		eax, ebx,
	"jnz",		LABEL ("end"),
	"add",		ebx,	   BASE (ebx, 127),
	"or",		ebx,	   IMM (1234),
	"xor",		ebx,	   BASE (ebx, 127),
	"cpuid",
	"push",		esi,
	"mov",		PTR (ebx), IMM (7),
	"mov",		PTR (ebx), eax,
	"mov",		eax,       PTR (ebx),
	"mov",		rax,       PTR (ebx),
	"mov",		r9,        PTR (r9),
	"push",		PTR (r9),
	"mov",		esp,       ebp,
	"mov",		ebp,       rsp,
	"jnz",		LABEL ("begin"),
	"call",		r10,
	"jmp",		r10,
	"jmp",		LABEL ("begin"),
	"nop",

	DEFINE_LABEL ("end"),

	"sal",		r10, IMM (17),
	"sal",		r10d, IMM (17),
	"rcl",		r10,   cl,
	"sal",		eax,   IMM (1),
	"pabsb",	xmm9,  BASE (rbx, 16),
	"pabsb",	mm7,   BASE (rbx, 16),
	"vpabsb",	xmm9,  BASE (rbx, 16),
	"xor",		rax, rax,
	"vpacksswb",	xmm12, xmm10, INDEX (rbx, 17, r10, 8),
	"vpacksswb",	xmm12, xmm10, INDEX (rbx, 17, rax, 8),
	"vpackusdw",	xmm12, xmm10, INDEX (rbx, 17, rax, 8),
	"vpackuswb",	xmm12, xmm10, INDEX (rbx, 17, rax, 8),
	"vpaddw",	xmm12, xmm10, xmm7,
	"mov",		r10, rdx,
	"palignr",	mm7,   PTR(r10), IMM(17),
	"vpalignr",	xmm7,  xmm8, PTR (r10), IMM (17),
	"vpandn",	xmm7,  xmm8, xmm9,
	"vpsubb",	xmm7,  xmm8, RIP_REL ("blah"),
	"vpaddb",	xmm3,  xmm3, xmm7,
	"mov",		eax,   ADDRESS (12345),
	"mov",		rax,   ADDRESS (12345),
	"mov",		rax,   BASE (rsp, 17),
	"mov",		rax,   PTR (r13),
	"mov",		rax,   INDEX (r13, 0, esp, 1),
	"mov",		eax,   ADDRESS (0xabcdef),
	"mov",		rax,   RIP (0x12345),
	"movabs",	r10,   IMM64 (0xfedeabefedeabeULL),
	"movabs",	rax,   IMM64 (0xfedeabefedeabeULL),
	"movabs",	rax,   IMM64 (&printf),
	"add",		eax,   eax,
	"dq",		IMM64 (printf),
	"dw",		IMM (12345),

	DEFINE_VALUE64 ("blah",		0xff00ff00ff00ff00ULL),
	DEFINE_VALUE64 ("hello",	"Hello World\n"),
	DEFINE_VALUE64 ("hello2",	"Hello again, World\n"),
	DEFINE_VALUE64 ("printf",	printf),
	DEFINE_VALUE64 ("retval",	"return value: %d\n"),

	NULL);

    code = x86_asm_emit (as);

    printf ("Size: %lu\n", sizeof (instructions));
    
    dummy();
    
    if (!code)
    {
	printf ("error\n");
    }
    else
    {
	typedef void (* func) (void);

	((func)code)();
    }

    return 0;
}