summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2015-06-12target-mips: remove misleading comments in translate_init.cLeon Alrae1-9/+0
PABITS are not hardcoded to 36 bits and we do not model 59 PABITS (which is the architectural limit) in QEMU. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-12target-mips: add MTHC0 and MFHC0 instructionsLeon Alrae3-0/+229
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access upper word of extended to 64-bits CP0 registers. In MIPS64, when CP0 destination register specified is the EntryLo0 or EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or EntryLo1. This is to compensate for RI and XI, which were shifted to bits 63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate functions for EntryLo0 and EntryLo1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-12target-mips: add CP0.PageGrain.ELPA supportLeon Alrae5-12/+42
CP0.PageGrain.ELPA enables support for large physical addresses. This field is encoded as follows: 0: Large physical address support is disabled. 1: Large physical address support is enabled. If this bit is a 1, the following changes occur to coprocessor 0 registers: - The PFNX field of the EntryLo0 and EntryLo1 registers is writable and concatenated with the PFN field to form the full page frame number. - Access to optional COP0 registers with PA extension, LLAddr, TagLo is defined. P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if XPA is disabled (CP0.PageGrain.ELPA = 0) then assume 32-bit Address Mode. In MIPS64 assume 36 as default PABITS (when CP0.PageGrain.ELPA = 0). env->PABITS value is constant and indicates maximum PABITS available on a core, whereas env->PAMask is calculated from env->PABITS and is also affected by CP0.PageGrain.ELPA. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-12target-mips: support Page Frame Number Extension fieldLeon Alrae1-6/+26
Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if large physical address is not supported. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-12target-mips: extend selected CP0 registers to 64-bits in MIPS32Leon Alrae4-42/+63
Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32. Introduce gen_move_low32() function which moves low 32 bits from 64-bit temp to GPR; it sign extends 32-bit value on MIPS64 and truncates on MIPS32. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-12target-mips: correct MFC0 for CP0.EntryLo in MIPS64Leon Alrae1-6/+6
CP0.EntryLo bits 31:30 have to be cleared. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-11net/dp8393x: fix hardware resetHervé Poussineau1-0/+1
Documentation is not clear of what happens when doing a hardware reset, but firmware expect all registers to be zero unless specified otherwise. This fixes reboot on MIPS Magnum. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11net/dp8393x: correctly reset in_use fieldHervé Poussineau1-1/+1
Don't write more than the field width, which is always 16 bit. Fixes network in NetBSD 5.1/arc Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11net/dp8393x: add load/save supportHervé Poussineau1-0/+12
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11net/dp8393x: add PROM to store MAC addressHervé Poussineau2-0/+19
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11net/dp8393x: QOM'ifyHervé Poussineau3-33/+67
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11net/dp8393x: use dp8393x_ prefix for all functionsHervé Poussineau1-39/+41
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11net/dp8393x: do not use old_mmio accessesHervé Poussineau1-85/+29
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11net/dp8393x: always calculate proper checksumsHervé Poussineau1-11/+1
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11dma/rc4030: convert to QOMHervé Poussineau3-43/+113
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11dma/rc4030: use trace events instead of custom loggingHervé Poussineau2-65/+22
Remove also unneeded debug logs. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11dma/rc4030: document register at offset 0x210Hervé Poussineau1-8/+8
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11dma/rc4030: do not use old_mmio accessesHervé Poussineau1-96/+16
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11dma/rc4030: use AddressSpace and address_space_rw in usersHervé Poussineau4-50/+42
Now that rc4030 internally uses an AddressSpace for DMA handling, make its root memory region public. This is especially usefull for dp8393x netcard, which now uses well known QEMU types and methods. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11dma/rc4030: create custom DMA address spaceHervé Poussineau1-37/+126
Add a new memory region in system address space where DMA address space definition (the 'translation table') belongs, so we can update on the fly the DMA address space. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11mips jazz: compile only in 64 bitHervé Poussineau7-18/+4
Remove now useless device models from other MIPS configurations We're now compiling 12 files less than before. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae6-7/+31
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit that is set by execution of an LL instruction, and thus when placed between an LL and SC sequence, will never cause the SC to fail. Presence of ERETNC is denoted by the Config5.LLB. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-11target-mips: Misaligned memory accesses for MSAYongbok Kim3-78/+102
MIPS SIMD Architecture vector loads and stores require misalignment support. MSA Memory access should work as an atomic operation. Therefore, it has to check validity of all addresses for a vector store access if it is spanning into two pages. Separating helper functions for each data format as format is known in translation. To use mmu_idx from cpu_mmu_index() instead of calculating it from hflag. Removing save_cpu_state() call in translation because it is able to use cpu_restore_state() on fault as GETRA() is passed. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> [leon.alrae@imgtec.com: remove unused do_* functions] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11softmmu: Add probe_write()Yongbok Kim2-0/+24
Probe for whether the specified guest write access is permitted. If it is not permitted then an exception will be taken in the same way as if this were a real write access (and we will not return). Otherwise the function will return, and there will be a valid entry in the TLB for this access. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11target-mips: Misaligned memory accesses for R6Yongbok Kim2-13/+28
Release 6 requires misaligned memory access support for all ordinary memory access instructions (for example, LW/SW, LWC1/SWC1). However misaligned support is not provided for certain special memory accesses such as atomics (for example, LL/SC). Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11mips_malta: provide ememsize env variable to kernelsPaul Burton1-6/+9
Commit 94c2b6aff43c (mips_malta: support up to 2GiB RAM) provided support for using over 256MB of RAM with the MIPS Malta board, including capping the memsize variable that QEMUs pseudo-bootloader provides to the kernel at 256MB in order to match YAMON. It didn't however provide the ememsize variable which kernels supporting memory outside of the unmapped address spaces (ie. EVA or highmem) may use to determine the true size of the RAM present in the system. Set ememsize to the size of RAM so that such kernels may use all available memory without the user having to manually specifying its size & location. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae4-156/+208
This relatively small architectural feature adds the following: FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are available. Config5.FRE: When enabled all single-precision FP arithmetic instructions, LWC1/LWXC1/MTC1, SWC1/SWXC1/MFC1 cause a Reserved Instructions exception. Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1 instructions. Enable the feature in MIPS64R6-generic CPU. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11target-mips: move group of functions above gen_load_fpr32()Leon Alrae1-60/+58
Move the "Tests" group of functions so that gen_load_fpr32() and gen_store_fpr32() can use generate_exception(). Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-10Merge remote-tracking branch 'remotes/kraxel/tags/pull-vga-20150610-1' into ↵Peter Maydell7-48/+1333
staging stdvga: factor out mmio subregion init virtio-gpu: add virtio gpu core code, 2d mode # gpg: Signature made Wed Jun 10 10:03:11 2015 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-vga-20150610-1: virtio-gpu/2d: add virtio gpu core code virtio: update headers, add virtio-gpu (2d) stdvga: factor out mmio subregion init stdvga: pass VGACommonState instead of PCIVGAState stdvga: fix offset in pci_vga_ioport_read Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-10Merge remote-tracking branch 'remotes/kraxel/tags/pull-fw_cfg-20150610-1' ↵Peter Maydell12-78/+163
into staging fw_cfg: drop write support, qemu cmdline support, bugfixes. bios-tables-test: fix smbios test. # gpg: Signature made Wed Jun 10 07:29:53 2015 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-fw_cfg-20150610-1: bios-tables-test: handle false-positive smbios signature matches fw_cfg: insert fw_cfg file blobs via qemu cmdline fw_cfg: prohibit insertion of duplicate fw_cfg file names fw_cfg: prevent selector key conflict fw_cfg: remove support for guest-side data writes fw_cfg: fix FW_CFG_BOOT_DEVICE update on ppc and sparc fw_cfg: add fw_cfg_modify_i16 (update) method QemuOpts: increase number of vm_config_groups Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-10Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20150609.0' ↵Peter Maydell7-0/+807
into staging Initial VFIO platform device support, v2 (Eric Auger, et al.) # gpg: Signature made Tue Jun 9 15:25:40 2015 BST using RSA key ID 3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" # gpg: aka "Alex Williamson <alex@shazbot.org>" # gpg: aka "Alex Williamson <alwillia@redhat.com>" # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" * remotes/awilliam/tags/vfio-update-20150609.0: hw/vfio/platform: calxeda xgmac device hw/vfio/platform: add irq assignment hw/vfio/platform: vfio-platform skeleton Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-10Merge remote-tracking branch ↵Peter Maydell1-0/+8
'remotes/stefanha/tags/CVE-2015-3209-pcnet-tx-buffer-fix-pull-request' into staging # gpg: Signature made Wed Jun 10 15:04:11 2015 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/CVE-2015-3209-pcnet-tx-buffer-fix-pull-request: pcnet: force the buffer access to be in bounds during tx Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-10pcnet: force the buffer access to be in bounds during txPetr Matousek1-0/+8
4096 is the maximum length per TMD and it is also currently the size of the relay buffer pcnet driver uses for sending the packet data to QEMU for further processing. With packet spanning multiple TMDs it can happen that the overall packet size will be bigger than sizeof(buffer), which results in memory corruption. Fix this by only allowing to queue maximum sizeof(buffer) bytes. This is CVE-2015-3209. [Fixed 3-space indentation to QEMU's 4-space coding standard. --Stefan] Signed-off-by: Petr Matousek <pmatouse@redhat.com> Reported-by: Matt Tait <matttait@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2015-06-10virtio-gpu/2d: add virtio gpu core codeGerd Hoffmann4-0/+1079
This patch adds the core code for virtio gpu emulation, covering 2d support. Written by Dave Airlie and Gerd Hoffmann. Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-06-10virtio: update headers, add virtio-gpu (2d)Gerd Hoffmann2-0/+205
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-06-10stdvga: factor out mmio subregion initGerd Hoffmann1-29/+30
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-06-10stdvga: pass VGACommonState instead of PCIVGAStateGerd Hoffmann1-22/+22
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-06-10stdvga: fix offset in pci_vga_ioport_readGerd Hoffmann1-3/+3
Simliar to pci_vga_ioport_write. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-06-10bios-tables-test: handle false-positive smbios signature matchesGabriel L. Somlo1-32/+44
It has been reported that sometimes the .rodata section of SeaBIOS, containing the constant string against which the SMBIOS signature ends up being compared, also falls within the guest f-segment. In that case, the test obviously fails, unless we continue searching for the *real* SMBIOS entry point. Rather than stopping at the first match for the SMBIOS signature ("_SM_") in the f-segment (0xF0000-0xFFFFF), continue scanning until either a valid entry point table is found, or the f-segment has been exhausted. Reported-by: Bruce Rogers <brogers@suse.com> Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Tested-by: Bruce Rogers <brogers@suse.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-06-10fw_cfg: insert fw_cfg file blobs via qemu cmdlineGabriel L. Somlo3-0/+95
Allow user supplied files to be inserted into the fw_cfg device before starting the guest. Since fw_cfg_add_file() already disallows duplicate fw_cfg file names, qemu will exit with an error message if the user supplies multiple blobs with the same fw_cfg file name, or if a blob name collides with a fw_cfg name programmatically added from within the QEMU source code. A warning message will be printed if the fw_cfg item name does not begin with the prefix "opt/", which is recommended for external, user provided blobs. Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-06-10fw_cfg: prohibit insertion of duplicate fw_cfg file namesGabriel L. Somlo2-6/+6
Exit with an error (instead of simply logging a trace event) whenever the same fw_cfg file name is added multiple times via one of the fw_cfg_add_file[_callback]() host-side API calls. Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-06-10fw_cfg: prevent selector key conflictGabriel L. Somlo1-0/+1
Enforce a single assignment of data for each distinct selector key. Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-06-10fw_cfg: remove support for guest-side data writesGabriel L. Somlo3-35/+1
From this point forward, any guest-side writes to the fw_cfg data register will be treated as no-ops. This patch also removes the unused host-side API function fw_cfg_add_callback(), which allowed the registration of a callback to be executed each time the guest completed a full overwrite of a given fw_cfg data item. Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-06-10fw_cfg: fix FW_CFG_BOOT_DEVICE update on ppc and sparcGabriel L. Somlo4-4/+4
On ppc, sparc, and sparc64, the value of the FW_CFG_BOOT_DEVICE 16bit fw_cfg entry is repeatedly modified from a series of callbacks, which currently results in the previous value's dynamically allocated memory being leaked. This patch switches updating to the new fw_cfg_modify_i16() call, which does not cause memory leaks. Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-06-10fw_cfg: add fw_cfg_modify_i16 (update) methodGabriel L. Somlo2-0/+11
Allow the ability to modify the value of an existing 16-bit integer fw_cfg item. Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-06-10QemuOpts: increase number of vm_config_groupsGerd Hoffmann1-1/+1
Adding the fw_cfg cmd line support patch by Gabriel L. Somlo hits the limit. Fix this by making the array larger. Cc: Gabriel L. Somlo <somlo@cmu.edu> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-06-09Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150609' into stagingPeter Maydell10-130/+126
Collected TCG patches # gpg: Signature made Tue Jun 9 15:06:18 2015 BST using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-tcg-20150609: tcg/optimize: rename tcg_constant_folding tcg/optimize: fold constant test in tcg_opt_gen_mov tcg/optimize: fold temp copies test in tcg_opt_gen_mov tcg/optimize: remove opc argument from tcg_opt_gen_mov tcg/optimize: remove opc argument from tcg_opt_gen_movi tcg: fix dead computation for repeated input arguments tcg: fix register allocation with two aliased dead inputs tcg: Handle MO_AMASK in tcg_dump_ops tcg: Mask TCGMemOp appropriately for indexing Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-09hw/vfio/platform: calxeda xgmac deviceEric Auger3-0/+102
The platform device class has become abstract. This patch introduces a calxeda xgmac device that derives from it. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2015-06-09tcg/optimize: rename tcg_constant_foldingAurelien Jarno1-6/+1
The tcg_constant_folding folding ends up doing all the optimizations (which is a good thing to avoid looping on all ops multiple time), so make it clear and just rename it tcg_optimize. Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <1433447607-31184-6-git-send-email-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-06-09tcg/optimize: fold constant test in tcg_opt_gen_movAurelien Jarno1-53/+36
Most of the calls to tcg_opt_gen_mov are preceeded by a test to check if the source temp is a constant. Fold that into the tcg_opt_gen_mov function. Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <1433495958-9508-1-git-send-email-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-04 05:21:22 +0000