diff options
| author | Mika Kuoppala <mika.kuoppala@intel.com> | 2016-03-30 14:07:14 +0300 |
|---|---|---|
| committer | Mika Kuoppala <mika.kuoppala@intel.com> | 2016-04-01 14:01:49 +0300 |
| commit | cf6a01743d914af98e7f69ddc65e3de4a60ba5ff (patch) | |
| tree | c0d5faf4641ca819643024afafd0bea0b22466b0 | |
| parent | fbb00e1d1a378e4222735231df61e19a67be34a1 (diff) | |
drm/i915: Don't use atomic wait on hsw lcpll setupwait_until
These functions mixes usage of atomic waits and sleeping waits.
Use the non atomic variant on waiting for FCLK for consistency.
There should be not much latency overhead as wait_for will poll
for first few interations over state.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d7722d22018d..c06089409bc3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9387,10 +9387,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, val |= LCPLL_CD_SOURCE_FCLK; I915_WRITE(LCPLL_CTL, val); - if (wait_until_reg_atomic(LCPLL_CTL, - LCPLL_CD_SOURCE_FCLK_DONE, - LCPLL_CD_SOURCE_FCLK_DONE, - 1)) + if (wait_until_reg_set(LCPLL_CTL, LCPLL_CD_SOURCE_FCLK_DONE, 1)) DRM_ERROR("Switching to FCLK failed\n"); val = I915_READ(LCPLL_CTL); @@ -9463,9 +9460,9 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) val &= ~LCPLL_CD_SOURCE_FCLK; I915_WRITE(LCPLL_CTL, val); - if (wait_until_reg_atomic(LCPLL_CTL, - LCPLL_CD_SOURCE_FCLK_DONE, - 0, 1)) + if (wait_until_reg_clr(LCPLL_CTL, + LCPLL_CD_SOURCE_FCLK_DONE, + 1)) DRM_ERROR("Switching back to LCPLL failed\n"); } |