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authorMika Kuoppala <mika.kuoppala@intel.com>2016-03-18 18:10:20 +0200
committerMika Kuoppala <mika.kuoppala@intel.com>2016-04-01 14:01:38 +0300
commitac745725ae48c125a9796318eb2c480d4d075ffd (patch)
tree90f528af78be3339c895e00a2dd602fec8beef07
parentb8d8dc44d8b90938c4997c3a192f860e3c974baf (diff)
drm/i915: Use wait_until_reg macros in bxt phy init
Use wait_until_reg instead of generic wait_for macro on these callsites. Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 2758622a5c2d..aade670cc836 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1740,8 +1740,8 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
* HW team confirmed that the time to reach phypowergood status is
* anywhere between 50 us and 100us.
*/
- if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
- (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
+ if (wait_until_reg(BXT_PORT_CL1CM_DW0(phy),
+ (PHY_RESERVED | PHY_POWER_GOOD), PHY_POWER_GOOD, 1)) {
DRM_ERROR("timeout during PHY%d power on\n", phy);
}
@@ -1810,8 +1810,8 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
* the corresponding calibrated value from PHY1, and disable
* the automatic calibration on PHY0.
*/
- if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
- 10))
+ if (wait_until_reg_set(BXT_PORT_REF_DW3(DPIO_PHY1), GRC_DONE,
+ 10))
DRM_ERROR("timeout waiting for PHY1 GRC\n");
val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));