diff options
author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2016-02-08 23:36:40 +0200 |
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committer | Mika Kuoppala <mika.kuoppala@intel.com> | 2016-03-22 18:29:40 +0200 |
commit | b2f08adb19fcb18fea7cda9908fa52e2b9db5e7f (patch) | |
tree | cccc8dca8c88deac2f3967a323cfd21ba6e5be37 | |
parent | 7e6c3f36563d133cff5b700d9c36b12ac2a0c643 (diff) |
drm/i915/vlv: Disable rps when changing frequencies
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d4f7f460f2f1..6780dda503da 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4466,10 +4466,20 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val) I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); if (val != dev_priv->rps.cur_freq) { + u32 ctrl; + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); + + ctrl = I915_READ(GEN6_RC_CONTROL); + I915_WRITE(GEN6_RC_CONTROL, 0); + vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); if (!IS_CHERRYVIEW(dev_priv)) gen6_set_rps_thresholds(dev_priv, val); + + I915_WRITE(GEN6_RC_CONTROL, ctrl); + POSTING_READ(GEN6_RC_CONTROL); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } |