From a13066aedfbc439ccdc1f31942623a8f3c83f988 Mon Sep 17 00:00:00 2001 From: Yang Rong Date: Thu, 29 Jan 2015 16:16:17 +0800 Subject: SKL: enable skl device. Add the intel_gpgpu_set_base_address_gen9 for SKL, the other functions are same as BDW in intel_GPGPU. And the SKL's backend just same as BDW. Should derive from GEN8 later. With this commit, some utests pass. Signed-off-by: Yang Rong Reviewed-by: He Junyan --- src/cl_command_queue.c | 2 +- src/intel/intel_driver.c | 4 ++- src/intel/intel_gpgpu.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 73 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/cl_command_queue.c b/src/cl_command_queue.c index f8435485..3c04d6d4 100644 --- a/src/cl_command_queue.c +++ b/src/cl_command_queue.c @@ -207,7 +207,7 @@ cl_command_queue_ND_range(cl_command_queue queue, /* Check that the user did not forget any argument */ TRY (cl_kernel_check_args, k); - if (ver == 7 || ver == 75 || ver == 8) + if (ver == 7 || ver == 75 || ver == 8 || ver == 9) TRY (cl_command_queue_ND_range_gen7, queue, k, work_dim, global_wk_off, global_wk_sz, local_wk_sz); else FATAL ("Unknown Gen Device"); diff --git a/src/intel/intel_driver.c b/src/intel/intel_driver.c index 21546d98..9e989b6f 100644 --- a/src/intel/intel_driver.c +++ b/src/intel/intel_driver.c @@ -170,7 +170,9 @@ intel_driver_init(intel_driver_t *driver, int dev_fd) else FATAL ("Unsupported Gen for emulation"); #else - if (IS_GEN8(driver->device_id)) + if (IS_GEN9(driver->device_id)) + driver->gen_ver = 9; + else if (IS_GEN8(driver->device_id)) driver->gen_ver = 8; else if (IS_GEN75(driver->device_id)) driver->gen_ver = 75; diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c index 479077c8..4c095b9c 100644 --- a/src/intel/intel_gpgpu.c +++ b/src/intel/intel_gpgpu.c @@ -347,6 +347,55 @@ intel_gpgpu_set_base_address_gen8(intel_gpgpu_t *gpgpu) ADVANCE_BATCH(gpgpu->batch); } +static void +intel_gpgpu_set_base_address_gen9(intel_gpgpu_t *gpgpu) +{ + const uint32_t def_cc = cl_gpgpu_get_cache_ctrl(); /* default Cache Control value */ + BEGIN_BATCH(gpgpu->batch, 19); + OUT_BATCH(gpgpu->batch, CMD_STATE_BASE_ADDRESS | 17); + /* 0, Gen State Mem Obj CC, Stateless Mem Obj CC, Stateless Access Write Back */ + OUT_BATCH(gpgpu->batch, 0 | (def_cc << 4) | (0 << 1)| BASE_ADDRESS_MODIFY); /* General State Base Addr */ + OUT_BATCH(gpgpu->batch, 0); + OUT_BATCH(gpgpu->batch, 0 | (def_cc << 16)); + /* 0, State Mem Obj CC */ + /* We use a state base address for the surface heap since IVB clamp the + * binding table pointer at 11 bits. So, we cannot use pointers directly while + * using the surface heap + */ + assert(gpgpu->aux_offset.surface_heap_offset % 4096 == 0); + OUT_RELOC(gpgpu->batch, gpgpu->aux_buf.bo, + I915_GEM_DOMAIN_SAMPLER, + I915_GEM_DOMAIN_SAMPLER, + gpgpu->aux_offset.surface_heap_offset + (0 | (def_cc << 4) | (0 << 1)| BASE_ADDRESS_MODIFY)); + OUT_BATCH(gpgpu->batch, 0); + OUT_RELOC(gpgpu->batch, gpgpu->aux_buf.bo, + I915_GEM_DOMAIN_RENDER, + I915_GEM_DOMAIN_RENDER, + (0 | (def_cc << 4) | (0 << 1)| BASE_ADDRESS_MODIFY)); /* Dynamic State Base Addr */ + OUT_BATCH(gpgpu->batch, 0); + OUT_BATCH(gpgpu->batch, 0 | (def_cc << 4) | BASE_ADDRESS_MODIFY); /* Indirect Obj Base Addr */ + OUT_BATCH(gpgpu->batch, 0); + //OUT_BATCH(gpgpu->batch, 0 | (def_cc << 4) | BASE_ADDRESS_MODIFY); /* Instruction Base Addr */ + OUT_RELOC(gpgpu->batch, (drm_intel_bo *)gpgpu->ker->bo, + I915_GEM_DOMAIN_INSTRUCTION, + I915_GEM_DOMAIN_INSTRUCTION, + 0 + (0 | (def_cc << 4) | (0 << 1)| BASE_ADDRESS_MODIFY)); + OUT_BATCH(gpgpu->batch, 0); + + OUT_BATCH(gpgpu->batch, 0xfffff000 | BASE_ADDRESS_MODIFY); + /* According to mesa i965 driver code, we must set the dynamic state access upper bound + * to a valid bound value, otherwise, the border color pointer may be rejected and you + * may get incorrect border color. This is a known hardware bug. */ + OUT_BATCH(gpgpu->batch, 0xfffff000 | BASE_ADDRESS_MODIFY); + OUT_BATCH(gpgpu->batch, 0xfffff000 | BASE_ADDRESS_MODIFY); + OUT_BATCH(gpgpu->batch, 0xfffff000 | BASE_ADDRESS_MODIFY); + /* Bindless surface state base address */ + OUT_BATCH(gpgpu->batch, (def_cc << 4) | BASE_ADDRESS_MODIFY); + OUT_BATCH(gpgpu->batch, 0); + OUT_BATCH(gpgpu->batch, 0xfffff000); + ADVANCE_BATCH(gpgpu->batch); +} + uint32_t intel_gpgpu_get_scratch_index_gen7(uint32_t size) { return size / 1024 - 1; } @@ -1054,7 +1103,8 @@ static uint32_t get_surface_type(intel_gpgpu_t *gpgpu, int index, cl_mem_object_ uint32_t surface_type; if (((IS_IVYBRIDGE(gpgpu->drv->device_id) || IS_HASWELL(gpgpu->drv->device_id) || - IS_BROADWELL(gpgpu->drv->device_id))) && + IS_BROADWELL(gpgpu->drv->device_id) || + IS_SKYLAKE(gpgpu->drv->device_id))) && index >= BTI_WORKAROUND_IMAGE_OFFSET + BTI_RESERVED_NUM && type == CL_MEM_OBJECT_IMAGE1D_ARRAY) surface_type = I965_SURFACE_2D; @@ -1960,6 +2010,24 @@ intel_set_gpgpu_callbacks(int device_id) intel_gpgpu_pipe_control = intel_gpgpu_pipe_control_gen7; return; } + if (IS_SKYLAKE(device_id)) { + cl_gpgpu_bind_image = (cl_gpgpu_bind_image_cb *) intel_gpgpu_bind_image_gen8; + intel_gpgpu_set_L3 = intel_gpgpu_set_L3_gen8; + cl_gpgpu_get_cache_ctrl = (cl_gpgpu_get_cache_ctrl_cb *)intel_gpgpu_get_cache_ctrl_gen8; + intel_gpgpu_get_scratch_index = intel_gpgpu_get_scratch_index_gen8; + intel_gpgpu_post_action = intel_gpgpu_post_action_gen7; //BDW need not restore SLM, same as gen7 + intel_gpgpu_read_ts_reg = intel_gpgpu_read_ts_reg_gen7; + intel_gpgpu_set_base_address = intel_gpgpu_set_base_address_gen9; + intel_gpgpu_setup_bti = intel_gpgpu_setup_bti_gen8; + intel_gpgpu_load_vfe_state = intel_gpgpu_load_vfe_state_gen8; + cl_gpgpu_walker = (cl_gpgpu_walker_cb *)intel_gpgpu_walker_gen8; + intel_gpgpu_build_idrt = intel_gpgpu_build_idrt_gen8; + intel_gpgpu_load_curbe_buffer = intel_gpgpu_load_curbe_buffer_gen8; + intel_gpgpu_load_idrt = intel_gpgpu_load_idrt_gen8; + cl_gpgpu_bind_sampler = (cl_gpgpu_bind_sampler_cb *) intel_gpgpu_bind_sampler_gen8; + intel_gpgpu_pipe_control = intel_gpgpu_pipe_control_gen7; + return; + } intel_gpgpu_set_base_address = intel_gpgpu_set_base_address_gen7; intel_gpgpu_load_vfe_state = intel_gpgpu_load_vfe_state_gen7; -- cgit v1.2.3