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path: root/src/mesa/drivers/dri/i965/brw_vec4_hs_visitor.cpp
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/*
 * Copyright © 2013 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

/**
 * \file brw_vec4_hs_visitor.cpp
 *
 * Tessellaton control shader specific code derived from the vec4_visitor class.
 */

#include "brw_vec4_hs_visitor.h"

const unsigned MAX_HS_INPUT_VERTICES = 32;

namespace brw {

vec4_hs_visitor::vec4_hs_visitor(const struct brw_compiler *compiler,
                                 void *log_data,
                                 struct brw_hs_compile *c,
                                 nir_shader *shader,
                                 void *mem_ctx,
                                 bool no_spills,
                                 int shader_time_index)
   : vec4_visitor(compiler, log_data, &c->key.tex, &c->prog_data.base,
                  shader, mem_ctx, no_spills, shader_time_index,
                  &c->input_vue_map),
     c(c)
{
}


void
vec4_hs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
{
   dst_reg *reg;

   switch (instr->intrinsic) {
   case nir_intrinsic_load_invocation_id:
      reg = &this->nir_system_values[SYSTEM_VALUE_INVOCATION_ID];
      if (reg->file == BAD_FILE) {
         *reg = *this->make_reg_for_system_value(SYSTEM_VALUE_INVOCATION_ID,
                                                 glsl_type::int_type);
      }
      break;
   default:
      vec4_visitor::nir_setup_system_value_intrinsic(instr);
   }
}

dst_reg *
vec4_hs_visitor::make_reg_for_system_value(int location, const glsl_type *type)
{
   dst_reg *reg = new(mem_ctx) dst_reg(this, type);

   switch (location) {
   case SYSTEM_VALUE_INVOCATION_ID:
      this->current_annotation = "initialize gl_InvocationID";
      emit(HS_OPCODE_GET_INSTANCE_ID, *reg);
      break;
   case SYSTEM_VALUE_PRIMITIVE_ID:
      break;
   default:
      assert(!"not reached");
      break;
   }

   return reg;
}


void
vec4_hs_visitor::setup_payload()
{
   int reg = 0;

   /* The payload always contains important data in r0, which contains
    * the URB handles that are passed on to the URB write at the end
    * of the thread.
    */
   reg++;

   /* r1.0 - r4.7 may contain the input control point URB handles,
    * which we use to pull vertex data.
    */

   //int num_vertices = ((brw_hs_prog_key *)key)->input_vertices;
   //int vertex_handle_regs = (num_vertices + 7) / 8;
   //reg += vertex_handle_regs;
   reg += 4;

   /* Push constants may start at r5.0 */

   reg = setup_uniforms(reg);

   /* But the first push constant is gl_PatchVerticesIn. */
   prog_data->base.dispatch_grf_start_reg++;
   reg++;

   this->first_non_payload_grf = reg;
}


void
vec4_hs_visitor::emit_prolog()
{
   nir_setup_system_values();
   emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS);
   emit(IF(BRW_PREDICATE_NORMAL));
   emit(BRW_OPCODE_DO);
}


void
vec4_hs_visitor::emit_thread_end()
{
   current_annotation = "thread end";


   vec4_instruction *inst;
   emit(ADD(nir_system_values[SYSTEM_VALUE_INVOCATION_ID], src_reg(nir_system_values[SYSTEM_VALUE_INVOCATION_ID]), src_reg(1)));
   inst = emit(CMP(dst_null_d(), src_reg(nir_system_values[SYSTEM_VALUE_INVOCATION_ID]), src_reg(((struct brw_hs_prog_data *) prog_data)->instances), BRW_CONDITIONAL_LE));
   inst = emit(BRW_OPCODE_WHILE);
   inst->predicate = BRW_PREDICATE_NORMAL;

   emit(BRW_OPCODE_ENDIF);

   if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
      emit_shader_time_end();

   /* XXX: need 0xf channel enables... */

   inst = emit(VS_OPCODE_URB_WRITE);
   inst->mlen = 1;   /* just the header, no data. */
   inst->urb_write_flags = BRW_URB_WRITE_EOT_COMPLETE;
}


void
vec4_hs_visitor::visit(ir_barrier *ir)
{
   /* XXX: Emit code to send BarrierMsg to the Message Gateway shared function */
}

void
vec4_hs_visitor::emit_input_urb_read(const dst_reg &dst,
                                     const src_reg &vertex_index,
                                     unsigned base_offset,
                                     const src_reg &indirect_offset)
{
   dst_reg temp(this, glsl_type::ivec4_type);
   temp.type = dst.type;

   /* Set up the message header to reference the proper parts of the URB */
   dst_reg header = dst_reg(this, glsl_type::uvec4_type);
   emit(HS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
        indirect_offset);

   /* Read into a temporary, ignoring writemasking. */
   vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
   read->offset = base_offset;
   read->mlen = 1;
   read->base_mrf = -1;

   /* Copy the temporary to the destination to deal with writemasking.
    *
    * Also attempt to deal with gl_PointSize being in the .w component.
    */
   if (read->offset == 0 && indirect_offset.file == BAD_FILE) {
      emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW)));
   } else {
      emit(MOV(dst, src_reg(temp)));
   }
}

void
vec4_hs_visitor::emit_output_urb_read(const dst_reg &dst,
                                      unsigned base_offset,
                                      const src_reg &indirect_offset)
{
   /* Set up the message header to reference the proper parts of the URB */
   dst_reg header = dst_reg(this, glsl_type::uvec4_type);
   emit(HS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
        src_reg(dst.writemask), indirect_offset);

   /* Read into a temporary, ignoring writemasking. */
   vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header));
   read->offset = base_offset;
   read->mlen = 1;
   read->base_mrf = -1;
}

void
vec4_hs_visitor::emit_urb_write(const src_reg &value,
                                unsigned writemask,
                                unsigned base_offset,
                                const src_reg &indirect_offset)
{
   src_reg message(this, glsl_type::uvec4_type, 2);
   vec4_instruction *inst;

   emit(HS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
        src_reg(writemask), indirect_offset);
   inst = emit(MOV(offset(dst_reg(retype(message, value.type)), 1), value));
   inst->force_writemask_all = true;

   inst = emit(HS_OPCODE_URB_WRITE, dst_null_f(), message);
   inst->offset = base_offset;
   inst->mlen = 2;
   inst->base_mrf = -1;
}

void
vec4_hs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
{
   switch (instr->intrinsic) {
   case nir_intrinsic_load_primitive_id:
      emit(HS_OPCODE_GET_PRIMITIVE_ID,
           get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
      break;
   case nir_intrinsic_load_patch_vertices_in:
      emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D),
               src_reg(retype(brw_vec1_grf(5, 0), BRW_REGISTER_TYPE_D))));
      break;
   case nir_intrinsic_load_per_vertex_input:
   case nir_intrinsic_load_per_vertex_input_indirect: {
      src_reg indirect_offset = get_nir_indirect_src(instr);
      src_reg vertex_index = get_nir_vertex_index_src(instr);
      unsigned imm_offset = instr->const_index[0];

      dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
      dst.writemask = brw_writemask_for_size(instr->num_components);

      emit_input_urb_read(dst, vertex_index, imm_offset, indirect_offset);
      break;
   }
   case nir_intrinsic_load_input:
   case nir_intrinsic_load_input_indirect:
      unreachable("nir_lower_io should never give us these.");
      break;
   case nir_intrinsic_load_output:
   case nir_intrinsic_load_output_indirect:
   case nir_intrinsic_load_per_vertex_output:
   case nir_intrinsic_load_per_vertex_output_indirect: {
      src_reg indirect_offset;
      unsigned imm_offset;

      get_patch_urb_offsets(instr, prog_data->vue_map.num_per_vertex_slots,
                            &imm_offset, &indirect_offset);

      dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
      dst.writemask = brw_writemask_for_size(instr->num_components);

      if (imm_offset == 0 && indirect_offset.file == BAD_FILE) {
         dst.type = BRW_REGISTER_TYPE_F;

         /* This is a read of gl_TessLevelInner[], which lives in the
          * Patch URB header.  The layout depends on the domain.
          */
         switch (c->key.ds_primitive_mode) {
         case GL_QUADS: {
            /* DWords 3-2 (reversed); use offset 0 and WZYX swizzle. */
            dst_reg tmp(this, glsl_type::vec4_type);
            emit_output_urb_read(tmp, 0, src_reg());
            emit(MOV(writemask(dst, WRITEMASK_XY),
                     swizzle(src_reg(tmp), BRW_SWIZZLE_WZYX)));
            break;
         }
         case GL_TRIANGLES:
            /* DWord 4; use offset 1 but normal swizzle/writemask. */
            emit_output_urb_read(writemask(dst, WRITEMASK_X), 1, src_reg());
            break;
         case GL_ISOLINES:
            /* All channels are undefined. */
            return;
         default:
            unreachable("Bogus tessellation domain");
         }
      } else if (imm_offset == 1 && indirect_offset.file == BAD_FILE) {
         dst.type = BRW_REGISTER_TYPE_F;

         /* This is a read of gl_TessLevelOuter[], which lives in the
          * high 4 DWords of the Patch URB header, in reverse order.
          */
         switch (c->key.ds_primitive_mode) {
         case GL_QUADS:
            dst.writemask = WRITEMASK_XYZW;
            break;
         case GL_TRIANGLES:
            dst.writemask = WRITEMASK_XYZ;
            break;
         case GL_ISOLINES:
            dst.writemask = WRITEMASK_XY;
            return;
         default:
            unreachable("Bogus tessellation domain");
         }

         dst_reg tmp(this, glsl_type::vec4_type);
         emit_output_urb_read(tmp, 1, src_reg());
         emit(MOV(dst, swizzle(src_reg(tmp), BRW_SWIZZLE_WZYX)));
      } else {
         emit_output_urb_read(dst, imm_offset, indirect_offset);
      }
      break;
   }
   case nir_intrinsic_store_output:
   case nir_intrinsic_store_output_indirect:
   case nir_intrinsic_store_per_vertex_output:
   case nir_intrinsic_store_per_vertex_output_indirect: {
      src_reg value = get_nir_src(instr->src[0]);
      src_reg indirect_offset;
      unsigned imm_offset;
      unsigned mask = brw_writemask_for_size(instr->num_components);
      unsigned swiz = BRW_SWIZZLE_XYZW;

      get_patch_urb_offsets(instr, prog_data->vue_map.num_per_vertex_slots,
                            &imm_offset, &indirect_offset);

      if (imm_offset == 0 && indirect_offset.file == BAD_FILE) {
         value.type = BRW_REGISTER_TYPE_F;

         /* This is a write to gl_TessLevelInner[], which lives in the
          * Patch URB header.  The layout depends on the domain.
          */
         switch (c->key.ds_primitive_mode) {
         case GL_QUADS:
            /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
             * We use an XXYX swizzle to reverse put .xy in the .wz
             * channels, and use a .zw writemask.
             */
            swiz = BRW_SWIZZLE4(0, 0, 1, 0);
            mask = WRITEMASK_ZW;
            break;
         case GL_TRIANGLES:
            /* gl_TessLevelInner[].x lives at DWord 4, so we set the
             * writemask to X and bump the URB offset by 1.
             */
            imm_offset = 1;
            mask = WRITEMASK_X;
            break;
         case GL_ISOLINES:
            /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
            return;
         default:
            unreachable("Bogus tessellation domain");
         }
      } else if (imm_offset == 1 && indirect_offset.file == BAD_FILE) {
         value.type = BRW_REGISTER_TYPE_F;

         /* This is a write to gl_TessLevelOuter[] which lives in the
          * Patch URB Header at DWords 4-7.  However, it's reversed, so
          * instead of .xyzw we have .wzyx.
          */
         swiz = BRW_SWIZZLE_WZYX;

         switch (c->key.ds_primitive_mode) {
         case GL_QUADS:
            mask = WRITEMASK_XYZW;
            break;
         case GL_TRIANGLES:
            mask = WRITEMASK_YZW;
            break;
         case GL_ISOLINES:
            mask = WRITEMASK_ZW;
            break;
         default:
            unreachable("Bogus tessellation domain");
         }
      }

      emit_urb_write(swizzle(value, swiz), mask,
                     imm_offset, indirect_offset);
      break;
   }

   case nir_intrinsic_barrier: {
      dst_reg header = dst_reg(this, glsl_type::uvec4_type);
      emit(HS_OPCODE_CREATE_BARRIER_HEADER, header);
      emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
      break;
   }

   default:
      vec4_visitor::nir_emit_intrinsic(instr);
   }
}


extern "C" const unsigned *
brw_hs_emit(struct brw_context *brw,
            struct gl_shader_program *shader_prog,
            struct brw_hs_compile *c,
            void *mem_ctx,
            int shader_time_index,
            unsigned *final_assembly_size)
{
   struct gl_shader *shader =
      shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL];
   const struct brw_compiler *compiler = brw->intelScreen->compiler;

   vec4_hs_visitor v(compiler, brw, c, shader->Program->nir, mem_ctx,
                     false /* no_spills */, shader_time_index);
   if (!v.run()) {
      shader_prog->LinkStatus = false;
      ralloc_strcat(&shader_prog->InfoLog, v.fail_msg);
      return NULL;
   }

   if (unlikely(INTEL_DEBUG & DEBUG_HS))
      v.dump_instructions();

   return brw_vec4_generate_assembly(compiler, brw, mem_ctx,
                                     shader->Program->nir,
                                     &c->prog_data.base, v.cfg,
                                     final_assembly_size);
}


} /* namespace brw */