path: root/src/mesa/drivers/dri/i965/brw_clip_util.c
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2014-06-26i965: Convert Gen4-5 clipping code to the new brw_inst API.Kenneth Graunke1-1/+1
Signed-off-by: Kenneth Graunke <> Reviewed-by: Matt Turner <>
2014-06-02i965: Put '_default_' in the name of functions that set default state.Kenneth Graunke1-7/+7
Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <> Reviewed-by: Matt Turner <>
2014-06-02i965: Eliminate brw_set_conditionalmod from the Gen4-5 compilers.Kenneth Graunke1-1/+1
With the predication changes eliminated, all this does is set the conditional modifier on a single instruction. Doing that directly is easy, and avoids mucking about with default state. Signed-off-by: Kenneth Graunke <> Reviewed-by: Matt Turner <>
2014-02-19i965: Have brw_imm_vf4() take the vector components as integer values.Francisco Jerez1-1/+1
Reviewed-by: Paul Berry <>
2014-01-17s/Tungsten Graphics/VMware/José Fonseca1-2/+2
Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the old copyright name is creating unnecessary confusion, hence this change. This was the sed script I used: $ cat tg2vmw.sed # Run as: # # git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed # # Rename copyrights s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g /Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./ s/TUNGSTEN GRAPHICS/VMWARE/g # Rename emails s/ s/ s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/ s/jrfonseca\? s/keithw\? s/ s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/ s/ # Remove dead links s@Tungsten Graphics ( Graphics@g # C string src/gallium/state_trackers/vega/api_misc.c s/"Tungsten Graphics, Inc"/"VMware, Inc"/ Reviewed-by: Brian Paul <>
2013-12-05i965: Drop trailing whitespace from the rest of the driver.Kenneth Graunke1-18/+18
Performed via: $ for file in *; do sed -i 's/ *//g'; done Signed-off-by: Kenneth Graunke <>
2013-08-26i965: Allow C++ type safety in the use of enum brw_urb_write_flags.Paul Berry1-1/+1
(From a suggestion by Francisco Jerez) If an enum represents a bitfield of flags, e.g.: enum E { A = 1, B = 2, C = 4, D = 8, }; then C++ normally prohibits statements like this: enum E x = A | B; because A and B are implicitly converted to ints before OR-ing them, and an int can't be stored in an enum without a type cast. C, on the other hand, allows an int to be implicitly converted to an enum without casting. In the past we've dealt with this situation by storing flag bitfields as ints. This avoids ugly casting at the expense of some type safety that C++ would normally have offered (e.g. we get no warning if we accidentally use the wrong enum type). However, we can get the best of both worlds if we override the | operator. The ugly casting is confined to the operator overload, and we still get the benefit of C++ making sure we don't use the wrong enum type. v2: Remove unnecessary comment and unnecessary use of "enum" keyword. Use static_cast. Reviewed-by: Chad Versace <> Reviewed-by: Francisco Jerez <>
2013-08-23i965: Combine 4 boolean args of brw_urb_WRITE into a flags bitfield.Paul Berry1-11/+8
The arguments to brw_urb_WRITE() were getting pretty unwieldy, and we have to add more flags to support geometry shaders anyhow. Also plumb these flags through brw_clip_emit_vue(), brw_set_urb_message(), and the vec4_instruction class. Reviewed-by: Ian Romanick <> Reviewed-by: Kenneth Graunke <> Reviewed-by: Matt Turner <>
2013-08-16i965: allow 8 user clip planes on CTG+Chris Forbes1-1/+6
There's no need to use a clip flag for NEGW on these gens, so no reason we can't just enable 8 planes. V2: - Bump (and document!) MAX_VERTS in the clip code. - Fix clip flag masks in the clip unit state and in the shader prolog - Move this to the end of the series for less breakage. Signed-off-by: Chris Forbes <> Reviewed-by: Paul Berry <>
2013-08-16i965/clip: Enable interpolation of clip distancesChris Forbes1-7/+3
Previously we had disabled interpolation of the clip distances as a special case, since they were unused. Signed-off-by: Chris Forbes <> Reviewed-by: Paul Berry <>
2013-08-01i965 Gen4/5: clip: Don't mangle flat varyingsChris Forbes1-21/+32
This patch ensures that integers will pass through unscathed. Doing (useless) computations on them is risky, especially when their bit patterns correspond to values like inf or nan. [V1-2]: Signed-off-by: Olivier Galibert <galibert at> Signed-off-by: Chris Forbes <> Reviewed-by: Paul Berry <> Reviewed-by: Kenneth Graunke <>
2013-08-01i965 Gen4/5: clip: Add support for noperspective varyingsChris Forbes1-10/+110
Adds support for interpolating noperspective varyings linearly in screen space when clipping. Based on Olivier Galibert's patch from last year: At this point all -fixed and -vertex interpolation tests work. V5: Add brw_clip_compile.has_noperspective_shading rather than another key flag. V6: Real bools. [V1-2]: Signed-off-by: Olivier Galibert <galibert at> Signed-off-by: Chris Forbes <> Acked-by: Paul Berry <> Reviewed-by: Kenneth Graunke <>
2013-08-01i965 Gen4/5: clip: correctly handle flat varyingsChris Forbes1-37/+9
Previously we only gave special treatment to the builtin color varyings. This patch adds support for arbitrary flat-shaded varyings, which is required for GLSL 1.30. Based on Olivier Galibert's patch from last year: V5: Move key.do_flat_shading to brw_clip_compile.has_flat_shading V6: Real bools. [V1-2]: Signed-off-by: Olivier Galibert <galibert at> Signed-off-by: Chris Forbes <> Reviewed-by: Kenneth Graunke <>
2013-07-09i965: Move intel_context::gen and gt fields to brw_context.Kenneth Graunke1-6/+5
Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <> Acked-by: Chris Forbes <> Acked-by: Paul Berry <> Acked-by: Anuj Phogat <>
2013-07-09i965: Replace intel_context:needs_ff_sync with intel->gen == 5.Kenneth Graunke1-2/+2
Technically, needs_ff_sync was set on Gen5+, but it was only consulted in the clipper threads and quad/lineloop decomposition code, which are both Gen4-5 only. So in reality it only identified Ironlake. The named flag doesn't really clarify things, and seems like overkill. Signed-off-by: Kenneth Graunke <> Acked-by: Chris Forbes <> Acked-by: Paul Berry <> Acked-by: Anuj Phogat <>
2013-03-23i965: Clarify nomenclature: vert_result -> varyingPaul Berry1-30/+29
This patch removes the terminology "vert_result" from the i965 driver, replacing it with "varying". The old terminology, "vert_result", was confusing because (a) it referred to the enum gl_vert_result, which no longer exists (it was replaced with gl_varying_slot), and (b) it implied a vertex output, but with the advent of geometry shaders, it could be either a vertex or a geometry output, depending what shaders are in use. The generic term "varying" is less confusing. No functional change. Reviewed-by: Ian Romanick <> Reviewed-by: Eric Anholt <> Reviewed-by: Kenneth Graunke <> v2: Whitespace fixes.
2013-03-15Replace gl_vert_result enum with gl_varying_slot.Paul Berry1-19/+19
This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <> Reviewed-by: Eric Anholt <> Tested-by: Brian Paul <>
2011-10-18intel: Convert from GLboolean to 'bool' from stdbool.h.Kenneth Graunke1-3/+3
I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <> Acked-by: Chad Versace <> Acked-by: Paul Berry <>
2011-09-28i965: don't intepolate clip distances on pre-GEN6.Paul Berry1-2/+8
On pre-GEN6 chips, the VUE slots set aside for clip distance aren't actually used, so there is no reason for the clipper to waste time interpolating them. When commit 62bad54727690bff5ed42a74272e7822fd36cdb6 changed the enum value used to represent these VUE slots, that caused the clipper to start interpolating them as an accidental side effect. This patch reverts to the old clipper behavior. Reviewed-by: Kenneth Graunke <>
2011-09-06i965: clip: Remove assumption about VUE header from brw_clip_interp_vertex()Paul Berry1-5/+8
Previously, brw_clip_interp_vertex() iterated only through the "non-header" elements of the VUE when performing interpolation (because header elements don't need interpolation). This code now refers exclusively to the VUE map to figure out which elements need interpolation, so that brw_clip_interp_vertex() doesn't need to know the header size. Reviewed-by: Eric Anholt <>
2011-09-06i965: clip: Convert computations to ..._to_offset() for clarity.Paul Berry1-10/+26
This patch replaces some ad-hoc computations using ATTR_SIZE and the offset[] array to use the VUE map functions brw_vert_result_to_offset() and brw_vue_slot_to_offset(). Reviewed-by: Eric Anholt <>
2011-09-06i965: clip: Add a function to determine whether a vert_result is in use.Paul Berry1-4/+4
Previously we would examine the offset[] array (since an offset of 0 meant "not in use"). This paves the way for removing the offset[] array. Reviewed-by: Eric Anholt <>
2011-09-06i965: clip: Rework brw_clip_interp_vertex() to use the VUE map.Paul Berry1-5/+5
Reviewed-by: Eric Anholt <>
2011-09-06i965: clip: Modify brw_clip_interp_vertex() to use the VUE map.Paul Berry1-2/+2
Reviewed-by: Eric Anholt <>
2011-09-06i965: clip: Move hpos_offest and ndc_offset into local functions.Paul Berry1-2/+6
The offsets within the VUE of HPOS and NDC are needed only in a few auxiliary clipping functions. This patch moves computation of those offsets into the functions that need them, and does the computation using the VUE map. Reviewed-by: Eric Anholt <>
2011-09-06i965: clip: rename header_position_offset to the more correct ndc_offset.Paul Berry1-1/+1
Reviewed-by: Eric Anholt <>
2011-05-17i965: Move IF stack handling into the EU abstraction layer/brw_compile.Kenneth Graunke1-3/+2
This hides the IF stack and back-patching of IF/ELSE instructions from each of the code generators, greatly simplifying the interface. Signed-off-by: Kenneth Graunke <> Reviewed-by: Eric Anholt <>
2010-07-26i965: Remove some duped register size/count definitionsEric Anholt1-5/+0
2010-07-19i965: Reduce repeated calculation of the attribute-offset-in-VUE.Eric Anholt1-10/+3
This cleans up some chipset dependency sprinkled around, and fixes a potential overflow of the attribute offset array for many vertex results.
2010-06-10mesa: rename src/mesa/shader/ to src/mesa/program/Brian Paul1-1/+1
2010-05-20i965: remove disabled code for cycling through MRF registers in clipping.Eric Anholt1-15/+2
The idea would be that you could have multiple send messages going on if nothing depended on the previous message's results and you used a different send message. The problem is that the later send requires the VUE handle returned by the first send's allocate anyway.
2010-05-18i965: Remove constant or ignored-by-hw args from FF sync message setup.Eric Anholt1-12/+7
2010-04-21intel: Clean up chipset name and gen num for IronlakeZhenyu Wang1-2/+2
Rename old IGDNG to Ironlake, and set 'gen' number for Ironlake as 5, so tracking the features with generation num instead of special is_ironlake flag. Reviewed-by: Eric Anholt <> Signed-off-by: Zhenyu Wang <>
2010-01-25Merge branch 'mesa_7_7_branch'Brian Paul1-1/+0
Conflicts: src/mesa/drivers/dri/intel/intel_screen.c src/mesa/drivers/dri/intel/intel_swapbuffers.c src/mesa/drivers/dri/r300/r300_emit.c src/mesa/drivers/dri/r300/r300_ioctl.c src/mesa/drivers/dri/r300/r300_tex.c src/mesa/drivers/dri/r300/r300_texstate.c
2010-01-22i965: Remove unnecessary headers.Vinson Lee1-1/+0
2009-12-22intel: Replace IS_G4X() across the driver with context structure usage.Eric Anholt1-3/+4
Saves ~2KB of code.
2009-12-22intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt1-2/+6
Saves ~480 bytes of code.
2009-07-30i965: Postpone ff_sync message in CLIP kernel on IGDNGXiang, Haihao1-12/+36
In addition, it guarantees ff_sync message is issued
2009-07-13i965: add support for new chipsetsXiang, Haihao1-0/+27
1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2008-09-18mesa: added "main/" prefix to includes, remove some -I paths from ↵Brian Paul1-4/+4
2008-08-21965: Fix incorrect backface cullingKrzysztof Czurylo1-3/+2
Fix incorrect backface culling for OGL tunnel in wireframe and point mode.
2008-01-25i965: valid message length includes message header.Xiang, Haihao1-1/+1
2007-08-31 optimize 965 clipZou Nan hai1-10/+2
1. increase clip thread number to 2 2. do cliptest for -rhw
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt1-0/+354
This driver comes from Tungsten Graphics, with a few further modifications by Intel.