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-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw.c3
-rw-r--r--src/mesa/drivers/dri/i965/gen6_blorp.cpp6
-rw-r--r--src/mesa/drivers/dri/i965/intel_batchbuffer.c12
4 files changed, 0 insertions, 22 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 8d098e6c3b..bba7d977f6 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -870,7 +870,6 @@ struct intel_batchbuffer {
drm_intel_bo *last_bo;
/** BO for post-sync nonzero writes for gen6 workaround. */
drm_intel_bo *workaround_bo;
- bool need_workaround_flush;
struct cached_batch_item *cached_items;
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 39da953e99..e4c24e92f2 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -276,9 +276,6 @@ static void brw_emit_prim(struct brw_context *brw,
OUT_BATCH(base_vertex_location);
ADVANCE_BATCH();
- /* Only used on Sandybridge; harmless to set elsewhere. */
- brw->batch.need_workaround_flush = true;
-
if (brw->always_flush_cache) {
intel_batchbuffer_emit_mi_flush(brw);
}
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 90b9fbb001..01db084cac 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -1010,9 +1010,6 @@ gen6_blorp_emit_primitive(struct brw_context *brw,
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
-
- /* Only used on Sandybridge; harmless to set elsewhere. */
- brw->batch.need_workaround_flush = true;
}
/**
@@ -1037,9 +1034,6 @@ gen6_blorp_exec(struct brw_context *brw,
uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
- /* Emit workaround flushes when we switch from drawing to blorping. */
- brw->batch.need_workaround_flush = true;
-
gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
gen6_emit_3dstate_sample_mask(brw,
params->dst.num_samples > 1 ?
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index caec312556..efa4ab6fbe 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -70,8 +70,6 @@ intel_batchbuffer_init(struct brw_context *brw)
4096, 4096);
}
- brw->batch.need_workaround_flush = true;
-
if (!brw->has_llc) {
brw->batch.cpu_map = malloc(BATCH_SZ);
brw->batch.map = brw->batch.cpu_map;
@@ -206,11 +204,6 @@ brw_new_batch(struct brw_context *brw)
brw->state.dirty.brw |= BRW_NEW_BATCH;
- /* Assume that the last command before the start of our batch was a
- * primitive, for safety.
- */
- brw->batch.need_workaround_flush = true;
-
brw->state_batch_count = 0;
brw->ib.type = -1;
@@ -610,17 +603,12 @@ gen7_emit_cs_stall_flush(struct brw_context *brw)
void
intel_emit_post_sync_nonzero_flush(struct brw_context *brw)
{
- if (!brw->batch.need_workaround_flush)
- return;
-
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STALL_AT_SCOREBOARD);
brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE,
brw->batch.workaround_bo, 0, 0, 0);
-
- brw->batch.need_workaround_flush = false;
}
/* Emit a pipelined flush to either flush render and texture cache for