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authorRoland Scheidegger <sroland@vmware.com>2012-07-27 03:43:11 +0200
committerRoland Scheidegger <sroland@vmware.com>2012-08-01 14:58:23 +0200
commitde694b6b10b7ce23a00cd7296a955f162704ee62 (patch)
treed21f7bb70b753491ab4fea0eb310ce304cd0dfc2 /src/mesa
parent5b88a2a22daae4d09596804d8edc6b8796d05150 (diff)
radeon/r200: fix bogus clears
There were several problems with these functions (which are a remnant of dri1 hyperz mostly - should bring it back somehow someday). First, it would always do a swrast clear if the buffer to clear was a fbo. Second, for buffers we wouldn't handle the clear (I guess aux/accum?) we would actually still have tried to clear that later even when we already cleared it with swrast.
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/r200/r200_ioctl.c37
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_ioctl.c37
2 files changed, 22 insertions, 52 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c
index e548fac328..faa9f16a37 100644
--- a/src/mesa/drivers/dri/r200/r200_ioctl.c
+++ b/src/mesa/drivers/dri/r200/r200_ioctl.c
@@ -57,8 +57,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
static void r200Clear( struct gl_context *ctx, GLbitfield mask )
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
- GLuint flags = 0;
- GLuint orig_mask = mask;
+ GLuint hwmask, swmask;
+ GLuint hwbits = BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT |
+ BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL |
+ BUFFER_BIT_COLOR0;
if ( R200_DEBUG & RADEON_IOCTL ) {
if (rmesa->radeon.sarea)
@@ -69,36 +71,19 @@ static void r200Clear( struct gl_context *ctx, GLbitfield mask )
radeonFlush( ctx );
- if ( mask & BUFFER_BIT_FRONT_LEFT ) {
- flags |= RADEON_FRONT;
- mask &= ~BUFFER_BIT_FRONT_LEFT;
- }
-
- if ( mask & BUFFER_BIT_BACK_LEFT ) {
- flags |= RADEON_BACK;
- mask &= ~BUFFER_BIT_BACK_LEFT;
- }
-
- if ( mask & BUFFER_BIT_DEPTH ) {
- flags |= RADEON_DEPTH;
- mask &= ~BUFFER_BIT_DEPTH;
- }
-
- if ( (mask & BUFFER_BIT_STENCIL) ) {
- flags |= RADEON_STENCIL;
- mask &= ~BUFFER_BIT_STENCIL;
- }
+ hwmask = mask & hwbits;
+ swmask = mask & ~hwbits;
- if ( mask ) {
+ if ( swmask ) {
if (R200_DEBUG & RADEON_FALLBACKS)
- fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
- _swrast_Clear( ctx, mask );
+ fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, swmask);
+ _swrast_Clear( ctx, swmask );
}
- if ( !flags )
+ if ( !hwmask )
return;
- radeonUserClear(ctx, orig_mask);
+ radeonUserClear(ctx, hwmask);
}
GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer,
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index 22118a7840..c6c8b05435 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -381,8 +381,10 @@ void radeonEmitAOS( r100ContextPtr rmesa,
static void radeonClear( struct gl_context *ctx, GLbitfield mask )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
- GLuint flags = 0;
- GLuint orig_mask = mask;
+ GLuint hwmask, swmask;
+ GLuint hwbits = BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT |
+ BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL |
+ BUFFER_BIT_COLOR0;
if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
rmesa->radeon.front_buffer_dirty = GL_TRUE;
@@ -394,36 +396,19 @@ static void radeonClear( struct gl_context *ctx, GLbitfield mask )
radeon_firevertices(&rmesa->radeon);
- if ( mask & BUFFER_BIT_FRONT_LEFT ) {
- flags |= RADEON_FRONT;
- mask &= ~BUFFER_BIT_FRONT_LEFT;
- }
-
- if ( mask & BUFFER_BIT_BACK_LEFT ) {
- flags |= RADEON_BACK;
- mask &= ~BUFFER_BIT_BACK_LEFT;
- }
-
- if ( mask & BUFFER_BIT_DEPTH ) {
- flags |= RADEON_DEPTH;
- mask &= ~BUFFER_BIT_DEPTH;
- }
-
- if ( (mask & BUFFER_BIT_STENCIL) ) {
- flags |= RADEON_STENCIL;
- mask &= ~BUFFER_BIT_STENCIL;
- }
+ hwmask = mask & hwbits;
+ swmask = mask & ~hwbits;
- if ( mask ) {
+ if ( swmask ) {
if (RADEON_DEBUG & RADEON_FALLBACKS)
- fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
- _swrast_Clear( ctx, mask );
+ fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, swmask);
+ _swrast_Clear( ctx, swmask );
}
- if ( !flags )
+ if ( !hwmask )
return;
- radeonUserClear(ctx, orig_mask);
+ radeonUserClear(ctx, hwmask);
}
void radeonInitIoctlFuncs( struct gl_context *ctx )