summaryrefslogtreecommitdiff
path: root/src/mesa/drivers/dri
diff options
context:
space:
mode:
authorKenneth Graunke <kenneth@whitecape.org>2012-08-08 09:41:19 -0700
committerKenneth Graunke <kenneth@whitecape.org>2012-08-08 17:15:21 -0700
commit5deb1d1a1f9e3354597569032af9bdf27d629cca (patch)
treedfd4e90cfcdcf9a780c4324b59db2897d4d7ce9f /src/mesa/drivers/dri
parentb0adbda75a092a92211bb519a395494532ddb17e (diff)
i965: Rework the extra flushes surrounding occlusion queries.
This removes the CS stall on Ivybridge. On Sandybridge, the depth stall needs to be preceded by a non-zero post-sync op, which requires a CS stall, which needs a stall at scoreboard. Emit the full workaround. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Eric Anholt <eric@anholt.net> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r--src/mesa/drivers/dri/i965/brw_queryobj.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 1e03d083da..b39f6441d1 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -91,14 +91,11 @@ static void
write_depth_count(struct intel_context *intel, drm_intel_bo *query_bo, int idx)
{
if (intel->gen >= 6) {
- BEGIN_BATCH(9);
-
- /* workaround: CS stall required before depth stall. */
- OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
- OUT_BATCH(PIPE_CONTROL_CS_STALL);
- OUT_BATCH(0); /* write address */
- OUT_BATCH(0); /* write data */
+ /* Emit Sandybridge workaround flush: */
+ if (intel->gen == 6)
+ intel_emit_post_sync_nonzero_flush(intel);
+ BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
OUT_BATCH(PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_WRITE_DEPTH_COUNT);