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authorJordan Justen <jordan.l.justen@intel.com>2013-07-09 15:19:55 -0700
committerJordan Justen <jordan.l.justen@intel.com>2013-08-04 11:52:37 -0700
commit08ef1dde1b7129463e8b603fd35df86646995232 (patch)
tree67c200263cc195823daf8cea66caedc34af29c79 /src/mesa/drivers/dri
parentbc1acaa4269f027b1b64a640f93df7a5c408cc17 (diff)
gen7 depth surface: calculate LOD being rendered to
This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r--src/mesa/drivers/dri/i965/gen7_blorp.cpp3
-rw-r--r--src/mesa/drivers/dri/i965/gen7_misc_state.c3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 618fe59fb6..2ab7c5787e 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -666,6 +666,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
uint32_t surftype;
unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
GLenum gl_target = params->depth.mt->target;
+ unsigned int lod;
brw_get_depthstencil_tile_masks(params->depth.mt,
params->depth.level,
@@ -688,6 +689,8 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
break;
}
+ lod = params->depth.level - params->depth.mt->first_level;
+
/* 3DSTATE_DEPTH_BUFFER */
{
uint32_t tile_x = draw_x & tile_mask_x;
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index f0f8b5dcc6..acbf79d1c3 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -46,6 +46,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
uint32_t surftype;
unsigned int depth = 1;
GLenum gl_target = GL_TEXTURE_2D;
+ unsigned int lod;
const struct intel_renderbuffer *irb = NULL;
const struct gl_renderbuffer *rb = NULL;
@@ -78,6 +79,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
break;
}
+ lod = irb ? irb->mt_level - irb->mt->first_level : 0;
+
/* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */
BEGIN_BATCH(7);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));