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authorKenneth Graunke <kenneth@whitecape.org>2014-10-13 23:45:07 -0700
committerKenneth Graunke <kenneth@whitecape.org>2014-10-15 08:44:54 -0700
commit39a5a60b57dcaa9392366a35169e554cdf157a1a (patch)
tree0f9e4494344f9848e944843070fc094d39baa2a8 /src/mesa/drivers/dri/i965/brw_fs_cse.cpp
parent159f93cf398fd301345f82ee0b10300cc523962b (diff)
i965: Allow CSE on Gen4-5 unary math.
Due to the implicit move-from-GRF, unary math looks a lot like the Gen6+ math instruction: it's a single instruction (SEND) with a GRF source. The difference is that it also implicitly clobbers a message register. The only visible effect is that CSE will remove the MRF-clobbering from later math operations. This should be fine; compute_to_mrf and remove_redundant_mrf_writes don't look at the values populated by implied writes, so they can't rely on those values being present. Less interference may actually help those passes make more progress. Binary math is still problematic, since it involves a separate MOV instruction to load the second operand. We continue disallowing CSE for binary math operations. total instructions in shared programs: 3340303 -> 3340100 (-0.01%) instructions in affected programs: 26927 -> 26724 (-0.75%) Nothing hurt, gained, or lost. ~6% reduction on a few shaders. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs_cse.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_cse.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
index 817fc1f1a1..801200118d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
@@ -99,7 +99,7 @@ is_expression(const fs_inst *const inst)
case SHADER_OPCODE_INT_REMAINDER:
case SHADER_OPCODE_SIN:
case SHADER_OPCODE_COS:
- return inst->mlen == 0;
+ return inst->mlen < 2;
case SHADER_OPCODE_LOAD_PAYLOAD:
return !is_copy_payload(inst);
default: