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authorChris Forbes <chrisf@ijw.co.nz>2013-07-07 22:51:02 +1200
committerChris Forbes <chrisf@ijw.co.nz>2013-08-16 07:24:56 +1200
commit4f739646b03f3d6e70461749ca0c0f3cb7390d75 (patch)
tree6eba3436526d5f4c795c6400093dac6d5e9ae582 /src/mesa/drivers/dri/i965/brw_clip_util.c
parentee0b8e0f063597c4f9dacaa3638ebd8875de151c (diff)
i965: allow 8 user clip planes on CTG+
There's no need to use a clip flag for NEGW on these gens, so no reason we can't just enable 8 planes. V2: - Bump (and document!) MAX_VERTS in the clip code. - Fix clip flag masks in the clip unit state and in the shader prolog - Move this to the end of the series for less breakage. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_clip_util.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_clip_util.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c
index 2ba4dcb65f..62172ecf6b 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_util.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_util.c
@@ -420,6 +420,7 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
{
struct brw_compile *p = &c->func;
struct brw_reg incoming = get_element_ud(c->reg.R0, 2);
+ struct brw_context *brw = p->brw;
/* Shift so that lowest outcode bit is rightmost:
*/
@@ -431,7 +432,11 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
/* Rearrange userclip outcodes so that they come directly after
* the fixed plane bits.
*/
- brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14));
+ if (brw->gen == 5 || brw->is_g4x)
+ brw_AND(p, tmp, incoming, brw_imm_ud(0xff<<14));
+ else
+ brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14));
+
brw_SHR(p, tmp, tmp, brw_imm_ud(8));
brw_OR(p, c->reg.planemask, c->reg.planemask, tmp);