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authorKenneth Graunke <kenneth@whitecape.org>2015-11-04 12:06:44 -0800
committerKenneth Graunke <kenneth@whitecape.org>2015-11-04 12:09:43 -0800
commita6b8e0a9ee77d84c76e8fafbb3928ebc668490e6 (patch)
tree319707b080a3d53efd5f82a7cb0c454ac2d10877
parent7c46408ee09f2e699d6b17563f06130e8da1ef53 (diff)
try to fix minimum DS URB entries
not observed to help anything
-rw-r--r--src/mesa/drivers/dri/i965/gen7_urb.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c
index 219fdcaad1..142500d6c1 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -288,9 +288,11 @@ gen7_upload_urb(struct brw_context *brw)
* [...]
* DS Number of URB Entries must be divisible by 8 if the DS URB Entry Allocation Size is
* programmed to a value less than 9, which is 10 512-bit URB entries.
+ *
+ * BDW PRM says 34.
*/
ds_chunks =
- ALIGN(MAX2(ds_granularity, 10) * ds_entry_size_bytes, chunk_size_bytes) /
+ ALIGN(MAX2(ds_granularity, 34) * ds_entry_size_bytes, chunk_size_bytes) /
chunk_size_bytes;
ds_wants =
ALIGN(brw->urb.max_ds_entries * ds_entry_size_bytes,