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authorKenneth Graunke <kenneth@whitecape.org>2015-11-09 16:38:28 -0800
committerKenneth Graunke <kenneth@whitecape.org>2015-11-09 16:38:28 -0800
commit09706bfdf22381e1318aa9293ab38d96a9590158 (patch)
treec6e5e99709f278408022b8da44b3d4ee68cc28ff
parent6bbbdadb5c940db69f146ed51555a30e032ad7b6 (diff)
LOOOOOOOP
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_hs_visitor.cpp11
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_nir.cpp3
-rw-r--r--src/mesa/drivers/dri/i965/gen8_hs_state.c2
3 files changed, 13 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_hs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_hs_visitor.cpp
index 7a49d95439..869dee89f5 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_hs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_hs_visitor.cpp
@@ -122,8 +122,10 @@ vec4_hs_visitor::setup_payload()
void
vec4_hs_visitor::emit_prolog()
{
+ nir_setup_system_values();
emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS);
emit(IF(BRW_PREDICATE_NORMAL));
+ emit(BRW_OPCODE_DO);
}
@@ -132,6 +134,13 @@ vec4_hs_visitor::emit_thread_end()
{
current_annotation = "thread end";
+
+ vec4_instruction *inst;
+ emit(ADD(nir_system_values[SYSTEM_VALUE_INVOCATION_ID], src_reg(nir_system_values[SYSTEM_VALUE_INVOCATION_ID]), src_reg(1)));
+ inst = emit(CMP(dst_null_d(), src_reg(nir_system_values[SYSTEM_VALUE_INVOCATION_ID]), src_reg(((struct brw_hs_prog_data *) prog_data)->instances), BRW_CONDITIONAL_LE));
+ inst = emit(BRW_OPCODE_WHILE);
+ inst->predicate = BRW_PREDICATE_NORMAL;
+
emit(BRW_OPCODE_ENDIF);
if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
@@ -139,7 +148,7 @@ vec4_hs_visitor::emit_thread_end()
/* XXX: need 0xf channel enables... */
- vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE);
+ inst = emit(VS_OPCODE_URB_WRITE);
inst->mlen = 1; /* just the header, no data. */
inst->urb_write_flags = BRW_URB_WRITE_EOT_COMPLETE;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index bbe1fc3377..c6eb1c9bca 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -41,7 +41,8 @@ vec4_visitor::emit_nir_code()
if (nir->num_uniforms > 0)
nir_setup_uniforms();
- nir_setup_system_values();
+ if (stage != MESA_SHADER_TESS_CTRL)
+ nir_setup_system_values();
/* get the main function and emit it */
nir_foreach_overload(nir, overload) {
diff --git a/src/mesa/drivers/dri/i965/gen8_hs_state.c b/src/mesa/drivers/dri/i965/gen8_hs_state.c
index 9ffb555f57..9ead8539f7 100644
--- a/src/mesa/drivers/dri/i965/gen8_hs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_hs_state.c
@@ -52,7 +52,7 @@ gen8_upload_hs_state(struct brw_context *brw)
OUT_BATCH(GEN7_HS_ENABLE |
GEN7_HS_STATISTICS_ENABLE |
(brw->max_hs_threads - 1) << GEN8_HS_MAX_THREADS_SHIFT |
- SET_FIELD(num_instances - 1, GEN7_HS_INSTANCE_COUNT));
+ SET_FIELD(1 - 1, GEN7_HS_INSTANCE_COUNT));
OUT_BATCH(stage_state->prog_offset);
OUT_BATCH(0);
if (prog_data->base.total_scratch) {