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authorMichel Dänzer <michel.daenzer@amd.com>2014-01-22 17:32:09 +0900
committerMichel Dänzer <michel@daenzer.net>2014-01-29 11:08:43 +0900
commitb4e14931a941f24dbd11d24653754acb48a95963 (patch)
tree6dfca91c7092111b328b9ca1087eb0d6c978c67f
parent67e385b3b79e86507211442152072cb86fc834fd (diff)
radeonsi: Pass VS resource descriptors to the HW ES shader stage as well
This makes sure constants and samplers work in the vertex shader even when a geometry shader is active. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
-rw-r--r--src/gallium/drivers/radeonsi/si_descriptors.c21
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.h3
-rw-r--r--src/gallium/drivers/radeonsi/si_shader.c12
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c31
-rw-r--r--src/gallium/drivers/radeonsi/si_state.h7
-rw-r--r--src/gallium/drivers/radeonsi/si_state_draw.c18
6 files changed, 58 insertions, 34 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 232a7d5aa5..2a54fcb54f 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -151,6 +151,11 @@ static void si_update_descriptors(struct si_context *sctx,
7 + /* copy */
(4 + desc->element_dw_size) * util_bitcount(desc->dirty_mask) + /* update */
4; /* pointer update */
+#if HAVE_LLVM >= 0x0305
+ if (desc->shader_userdata_reg >= R_00B130_SPI_SHADER_USER_DATA_VS_0 &&
+ desc->shader_userdata_reg < R_00B230_SPI_SHADER_USER_DATA_GS_0)
+ desc->atom.num_dw += 4; /* second pointer update */
+#endif
desc->atom.dirty = true;
/* The descriptors are read with the K cache. */
sctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
@@ -170,6 +175,19 @@ static void si_emit_shader_pointer(struct si_context *sctx,
radeon_emit(cs, (desc->shader_userdata_reg - SI_SH_REG_OFFSET) >> 2);
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
+
+#if HAVE_LLVM >= 0x0305
+ if (desc->shader_userdata_reg >= R_00B130_SPI_SHADER_USER_DATA_VS_0 &&
+ desc->shader_userdata_reg < R_00B230_SPI_SHADER_USER_DATA_GS_0) {
+ radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
+ radeon_emit(cs, (desc->shader_userdata_reg +
+ (R_00B330_SPI_SHADER_USER_DATA_ES_0 -
+ R_00B130_SPI_SHADER_USER_DATA_VS_0) -
+ SI_SH_REG_OFFSET) >> 2);
+ radeon_emit(cs, va);
+ radeon_emit(cs, va >> 32);
+ }
+#endif
}
static void si_emit_descriptors(struct si_context *sctx,
@@ -242,8 +260,6 @@ static void si_emit_descriptors(struct si_context *sctx,
static unsigned si_get_shader_user_data_base(unsigned shader)
{
switch (shader) {
- case SI_SHADER_EXPORT:
- return R_00B330_SPI_SHADER_USER_DATA_ES_0;
case PIPE_SHADER_VERTEX:
return R_00B130_SPI_SHADER_USER_DATA_VS_0;
case PIPE_SHADER_GEOMETRY:
@@ -508,7 +524,6 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
/* The stride field in the resource descriptor has 14 bits */
assert(stride < (1 << 14));
- slot += NUM_PIPE_CONST_BUFFERS + 1;
assert(slot < buffers->num_buffers);
pipe_resource_reference(&buffers->buffers[slot], NULL);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 45a8f67d67..d63a52b0af 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -76,8 +76,7 @@ struct si_surface {
#define SI_NUM_ATOMS(sctx) (sizeof((sctx)->atoms)/sizeof((sctx)->atoms.array[0]))
-#define SI_SHADER_EXPORT (PIPE_SHADER_GEOMETRY+1)
-#define SI_NUM_SHADERS (SI_SHADER_EXPORT+1)
+#define SI_NUM_SHADERS (PIPE_SHADER_GEOMETRY+1)
struct si_context {
struct r600_common_context b;
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 999ccf2568..2f9993c4c8 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -321,8 +321,7 @@ static LLVMValueRef fetch_input_gs(
/* Load the ESGS ring resource descriptor */
t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
- lp_build_const_int32(gallivm,
- NUM_PIPE_CONST_BUFFERS + 1));
+ lp_build_const_int32(gallivm, SI_RING_ESGS));
args[0] = t_list;
args[1] = vtx_offset;
@@ -1200,8 +1199,7 @@ static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
/* Load the ESGS ring resource descriptor */
t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
- lp_build_const_int32(gallivm,
- NUM_PIPE_CONST_BUFFERS + 1));
+ lp_build_const_int32(gallivm, SI_RING_ESGS));
for (i = 0; i < es->noutput; i++) {
LLVMValueRef *out_ptr =
@@ -1913,8 +1911,7 @@ static void si_llvm_emit_vertex(
/* Load the GSVS ring resource descriptor */
t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
- lp_build_const_int32(gallivm,
- NUM_PIPE_CONST_BUFFERS + 2));
+ lp_build_const_int32(gallivm, SI_RING_GSVS));
if (shader->noutput == 0) {
struct tgsi_parse_context *parse = &si_shader_ctx->parse;
@@ -2378,8 +2375,7 @@ static int si_generate_gs_copy_shader(struct si_context *sctx,
/* Load the GSVS ring resource descriptor */
t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
- lp_build_const_int32(gallivm,
- NUM_PIPE_CONST_BUFFERS + 1));
+ lp_build_const_int32(gallivm, SI_RING_GSVS));
args[0] = t_list;
args[1] = lp_build_mul_imm(uint,
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index aa151238c2..5020547e21 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2809,13 +2809,13 @@ static void si_set_sampler_views(struct pipe_context *ctx,
sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
}
-static struct si_pm4_state *si_set_sampler_states(struct si_context *sctx, unsigned count,
- void **states,
- struct si_textures_info *samplers,
- unsigned user_data_reg)
+static void si_set_sampler_states(struct si_context *sctx,
+ struct si_pm4_state *pm4,
+ unsigned count, void **states,
+ struct si_textures_info *samplers,
+ unsigned user_data_reg)
{
struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
- struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
uint32_t *border_color_table = NULL;
int i, j;
@@ -2880,25 +2880,31 @@ static struct si_pm4_state *si_set_sampler_states(struct si_context *sctx, unsig
out:
samplers->n_samplers = count;
- return pm4;
}
static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
{
struct si_context *sctx = (struct si_context *)ctx;
- struct si_pm4_state *pm4;
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
- pm4 = si_set_sampler_states(sctx, count, states, &sctx->samplers[PIPE_SHADER_VERTEX],
+ si_set_sampler_states(sctx, pm4, count, states,
+ &sctx->samplers[PIPE_SHADER_VERTEX],
R_00B130_SPI_SHADER_USER_DATA_VS_0);
+#if HAVE_LLVM >= 0x0305
+ si_set_sampler_states(sctx, pm4, count, states,
+ &sctx->samplers[PIPE_SHADER_VERTEX],
+ R_00B330_SPI_SHADER_USER_DATA_ES_0);
+#endif
si_pm4_set_state(sctx, vs_sampler, pm4);
}
static void si_bind_gs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
{
struct si_context *sctx = (struct si_context *)ctx;
- struct si_pm4_state *pm4;
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
- pm4 = si_set_sampler_states(sctx, count, states, &sctx->samplers[PIPE_SHADER_GEOMETRY],
+ si_set_sampler_states(sctx, pm4, count, states,
+ &sctx->samplers[PIPE_SHADER_GEOMETRY],
R_00B230_SPI_SHADER_USER_DATA_GS_0);
si_pm4_set_state(sctx, gs_sampler, pm4);
}
@@ -2906,9 +2912,10 @@ static void si_bind_gs_sampler_states(struct pipe_context *ctx, unsigned count,
static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
{
struct si_context *sctx = (struct si_context *)ctx;
- struct si_pm4_state *pm4;
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
- pm4 = si_set_sampler_states(sctx, count, states, &sctx->samplers[PIPE_SHADER_FRAGMENT],
+ si_set_sampler_states(sctx, pm4, count, states,
+ &sctx->samplers[PIPE_SHADER_FRAGMENT],
R_00B030_SPI_SHADER_USER_DATA_PS_0);
si_pm4_set_state(sctx, ps_sampler, pm4);
}
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index e24c0bb0cc..f7082f5df4 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -114,8 +114,11 @@ union si_state {
#define NUM_SAMPLER_VIEWS (FMASK_TEX_OFFSET+NUM_TEX_UNITS)
#define NUM_SAMPLER_STATES NUM_TEX_UNITS
-#define NUM_PIPE_CONST_BUFFERS 16
-#define NUM_CONST_BUFFERS 19
+#define NUM_PIPE_CONST_BUFFERS 16
+#define SI_RING_ESGS 17
+#define SI_RING_GSVS 18
+#define NUM_CONST_BUFFERS (SI_RING_GSVS + 1)
+
/* This represents resource descriptors in memory, such as buffer resources,
* image resources, and sampler states.
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 7ccfb58d70..7c8fe76695 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -569,12 +569,15 @@ static void si_init_gs_rings(struct si_context *sctx)
sctx->gsvs_ring.buffer_size / 256);
}
- si_set_ring_buffer(&sctx->b.b, SI_SHADER_EXPORT, 0, &sctx->esgs_ring,
- 0, sctx->esgs_ring.buffer_size, true, true, 4, 64);
- si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, 0, &sctx->esgs_ring,
- 0, sctx->esgs_ring.buffer_size, false, false, 0, 0);
- si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, 0, &sctx->gsvs_ring,
- 0, sctx->gsvs_ring.buffer_size, false, false, 0, 0);
+ si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
+ &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
+ true, true, 4, 64);
+ si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
+ &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
+ false, false, 0, 0);
+ si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
+ &sctx->gsvs_ring, 0, sctx->gsvs_ring.buffer_size,
+ false, false, 0, 0);
}
static void si_update_derived_state(struct si_context *sctx)
@@ -620,7 +623,8 @@ static void si_update_derived_state(struct si_context *sctx)
sctx->b.flags |= R600_CONTEXT_VGT_FLUSH;
si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
- si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, 1, &sctx->gsvs_ring,
+ si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
+ &sctx->gsvs_ring,
sctx->gs_shader->current->shader.gs_max_out_vertices *
sctx->gs_shader->current->shader.noutput * 16,
64, true, true, 4, 16);