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authorKenneth Graunke <kenneth@whitecape.org>2014-08-31 10:26:34 -0700
committerKenneth Graunke <kenneth@whitecape.org>2015-01-10 19:27:10 -0800
commit91ae8e997fc8645d27815cb59903b44059597bfd (patch)
tree861a3275f4730afeb81e9b893c45554f8bc99f0c
parent199e7288363e311f8727cda4defa86834d2034ed (diff)
i965: Enable replicated color clears on Ironlake.
Now that this is done via Meta and not BLORP, we can trivially enable it on Ironlake as well. We could probably enable it on G45 as well, but we currently don't even try to compile SIMD16 programs on G45 since there's only one kernel start pointer, and you have to use jumps. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
-rw-r--r--src/mesa/drivers/dri/i965/brw_clear.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 1231420480..f4ecefd15f 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -242,7 +242,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
}
/* Clear color buffers with fast clear or at least rep16 writes. */
- if (brw->gen >= 6 && brw->gen < 9 && (mask & BUFFER_BITS_COLOR)) {
+ if (brw->gen >= 5 && brw->gen < 9 && (mask & BUFFER_BITS_COLOR)) {
if (brw_meta_fast_clear(brw, fb, mask, partial_clear)) {
debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
mask &= ~BUFFER_BITS_COLOR;