diff options
author | Anuj Phogat <anuj.phogat@gmail.com> | 2021-04-07 13:22:19 -0700 |
---|---|---|
committer | Marge Bot <eric+marge@anholt.net> | 2021-04-20 20:06:34 +0000 |
commit | 4f42b28cc331e1fd0b7bd86542b481b924c5e680 (patch) | |
tree | a0c34843c5c6b2a7e3caae4e8da38400942dae2c | |
parent | 07eec673fce98da0c1dbfdc1360416d85f66d46b (diff) |
intel: Rename gen_{mapped, clflush, invalidate} prefix to intel_{..}
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965
grep -E "gen_" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_\(mapped\|clflush\|invalidate\|shader\)/intel_\1/g"
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
-rw-r--r-- | src/gallium/drivers/iris/iris_bufmgr.c | 4 | ||||
-rw-r--r-- | src/intel/common/intel_aux_map.c | 4 | ||||
-rw-r--r-- | src/intel/common/intel_aux_map.h | 2 | ||||
-rw-r--r-- | src/intel/common/intel_buffer_alloc.h | 2 | ||||
-rw-r--r-- | src/intel/common/intel_clflush.h | 8 | ||||
-rw-r--r-- | src/intel/tools/intel_sanitize_gpu.c | 2 | ||||
-rw-r--r-- | src/intel/vulkan/anv_device.c | 6 | ||||
-rw-r--r-- | src/intel/vulkan/anv_wsi.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_bufmgr.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_disk_cache.c | 6 |
10 files changed, 19 insertions, 19 deletions
diff --git a/src/gallium/drivers/iris/iris_bufmgr.c b/src/gallium/drivers/iris/iris_bufmgr.c index cd6f1de0ca3..99dd2e79135 100644 --- a/src/gallium/drivers/iris/iris_bufmgr.c +++ b/src/gallium/drivers/iris/iris_bufmgr.c @@ -1070,7 +1070,7 @@ iris_bo_map_cpu(struct pipe_debug_callback *dbg, * LLC entirely requiring us to keep dirty pixels for the scanout * out of any cache.) */ - gen_invalidate_range(bo->map_cpu, bo->size); + intel_invalidate_range(bo->map_cpu, bo->size); } return bo->map_cpu; @@ -1858,7 +1858,7 @@ intel_aux_map_buffer_free(void *driver_ctx, struct intel_buffer *buffer) free(buffer); } -static struct gen_mapped_pinned_buffer_alloc aux_map_allocator = { +static struct intel_mapped_pinned_buffer_alloc aux_map_allocator = { .alloc = intel_aux_map_buffer_alloc, .free = intel_aux_map_buffer_free, }; diff --git a/src/intel/common/intel_aux_map.c b/src/intel/common/intel_aux_map.c index ba71c270df4..20d2548d697 100644 --- a/src/intel/common/intel_aux_map.c +++ b/src/intel/common/intel_aux_map.c @@ -101,7 +101,7 @@ struct aux_map_buffer { struct intel_aux_map_context { void *driver_ctx; pthread_mutex_t mutex; - struct gen_mapped_pinned_buffer_alloc *buffer_alloc; + struct intel_mapped_pinned_buffer_alloc *buffer_alloc; uint32_t num_buffers; struct list_head buffers; uint64_t level3_base_addr; @@ -199,7 +199,7 @@ intel_aux_map_get_state_num(struct intel_aux_map_context *ctx) struct intel_aux_map_context * intel_aux_map_init(void *driver_ctx, - struct gen_mapped_pinned_buffer_alloc *buffer_alloc, + struct intel_mapped_pinned_buffer_alloc *buffer_alloc, const struct intel_device_info *devinfo) { struct intel_aux_map_context *ctx; diff --git a/src/intel/common/intel_aux_map.h b/src/intel/common/intel_aux_map.h index d09ae06852f..4884bc8abdf 100644 --- a/src/intel/common/intel_aux_map.h +++ b/src/intel/common/intel_aux_map.h @@ -53,7 +53,7 @@ struct intel_device_info; struct intel_aux_map_context * intel_aux_map_init(void *driver_ctx, - struct gen_mapped_pinned_buffer_alloc *buffer_alloc, + struct intel_mapped_pinned_buffer_alloc *buffer_alloc, const struct intel_device_info *devinfo); void diff --git a/src/intel/common/intel_buffer_alloc.h b/src/intel/common/intel_buffer_alloc.h index d23faef46dd..6b844271bc5 100644 --- a/src/intel/common/intel_buffer_alloc.h +++ b/src/intel/common/intel_buffer_alloc.h @@ -37,7 +37,7 @@ struct intel_buffer { void *driver_bo; }; -struct gen_mapped_pinned_buffer_alloc { +struct intel_mapped_pinned_buffer_alloc { struct intel_buffer * (*alloc)(void *driver_ctx, uint32_t size); void (*free)(void *driver_ctx, struct intel_buffer *buffer); }; diff --git a/src/intel/common/intel_clflush.h b/src/intel/common/intel_clflush.h index f3102e952d4..7c6aaf8f2df 100644 --- a/src/intel/common/intel_clflush.h +++ b/src/intel/common/intel_clflush.h @@ -28,7 +28,7 @@ #define CACHELINE_MASK 63 static inline void -gen_clflush_range(void *start, size_t size) +intel_clflush_range(void *start, size_t size) { void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK); void *end = start + size; @@ -43,13 +43,13 @@ static inline void intel_flush_range(void *start, size_t size) { __builtin_ia32_mfence(); - gen_clflush_range(start, size); + intel_clflush_range(start, size); } static inline void -gen_invalidate_range(void *start, size_t size) +intel_invalidate_range(void *start, size_t size) { - gen_clflush_range(start, size); + intel_clflush_range(start, size); /* Modern Atom CPUs (Baytrail+) have issues with clflush serialization, * where mfence is not a sufficient synchronization barrier. We must diff --git a/src/intel/tools/intel_sanitize_gpu.c b/src/intel/tools/intel_sanitize_gpu.c index bda540d6d75..492d1b6162a 100644 --- a/src/intel/tools/intel_sanitize_gpu.c +++ b/src/intel/tools/intel_sanitize_gpu.c @@ -189,7 +189,7 @@ padding_is_good(int fd, uint32_t handle) * if the bo is not cache coherent we likely need to * invalidate the cache lines to get it. */ - gen_invalidate_range(mapped, PADDING_SIZE); + intel_invalidate_range(mapped, PADDING_SIZE); expected_value = handle & 0xFF; for (uint32_t i = 0; i < PADDING_SIZE; ++i) { diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 1e18736cc7c..abf1bae0441 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -2750,7 +2750,7 @@ anv_device_init_trivial_batch(struct anv_device *device) anv_batch_emit(&batch, GFX7_MI_NOOP, noop); if (!device->info.has_llc) - gen_clflush_range(batch.start, batch.next - batch.start); + intel_clflush_range(batch.start, batch.next - batch.start); return VK_SUCCESS; } @@ -2866,7 +2866,7 @@ intel_aux_map_buffer_free(void *driver_ctx, struct intel_buffer *buffer) free(buf); } -static struct gen_mapped_pinned_buffer_alloc aux_map_allocator = { +static struct intel_mapped_pinned_buffer_alloc aux_map_allocator = { .alloc = intel_aux_map_buffer_alloc, .free = intel_aux_map_buffer_free, }; @@ -4101,7 +4101,7 @@ clflush_mapped_ranges(struct anv_device *device, if (ranges[i].offset >= mem->map_size) continue; - gen_clflush_range(mem->map + ranges[i].offset, + intel_clflush_range(mem->map + ranges[i].offset, MIN2(ranges[i].size, mem->map_size - ranges[i].offset)); } } diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c index d452cf6cf61..04d85d99d67 100644 --- a/src/intel/vulkan/anv_wsi.c +++ b/src/intel/vulkan/anv_wsi.c @@ -295,7 +295,7 @@ VkResult anv_QueuePresentKHR( if (device->debug_frame_desc) { device->debug_frame_desc->frame_id++; if (!device->info.has_llc) { - gen_clflush_range(device->debug_frame_desc, + intel_clflush_range(device->debug_frame_desc, sizeof(*device->debug_frame_desc)); } } diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c index 4da6f116fb6..2e5ede3930d 100644 --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c @@ -1113,7 +1113,7 @@ brw_bo_map_cpu(struct brw_context *brw, struct brw_bo *bo, unsigned flags) * LLC entirely requiring us to keep dirty pixels for the scanout * out of any cache.) */ - gen_invalidate_range(bo->map_cpu, bo->size); + intel_invalidate_range(bo->map_cpu, bo->size); } return bo->map_cpu; diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c b/src/mesa/drivers/dri/i965/brw_disk_cache.c index 2caf59ec081..e94cf3220a6 100644 --- a/src/mesa/drivers/dri/i965/brw_disk_cache.c +++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c @@ -53,7 +53,7 @@ debug_enabled_for_stage(gl_shader_stage stage) } static void -gen_shader_sha1(struct gl_program *prog, gl_shader_stage stage, +intel_shader_sha1(struct gl_program *prog, gl_shader_stage stage, void *key, unsigned char *out_sha1) { char sha1_buf[41]; @@ -120,7 +120,7 @@ read_and_upload(struct brw_context *brw, struct disk_cache *cache, */ prog_key.base.program_string_id = 0; - gen_shader_sha1(prog, stage, &prog_key, binary_sha1); + intel_shader_sha1(prog, stage, &prog_key, binary_sha1); size_t buffer_size; uint8_t *buffer = disk_cache_get(cache, binary_sha1, &buffer_size); @@ -280,7 +280,7 @@ write_program_data(struct brw_context *brw, struct gl_program *prog, unsigned char sha1[20]; char buf[41]; - gen_shader_sha1(prog, stage, key, sha1); + intel_shader_sha1(prog, stage, key, sha1); _mesa_sha1_format(buf, sha1); if (brw->ctx._Shader->Flags & GLSL_CACHE_INFO) { fprintf(stderr, "putting binary in cache: %s\n", buf); |