summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2017-05-03drm/amd/display: Assign stream to map before we need itamd-staging-dc-4.9Harry Wentland1-4/+2
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2017-05-03drm/amd/display: Get dprefclk ss percentage from vbiosHersen Wu3-48/+51
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: move drr_params definition to TGTony Cheng2-11/+7
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
2017-05-03drm/amd/display: Disable cursor on video surface.Yongqiang Sun1-0/+4
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: Add support for FreeSync on eDP to moduleEric Cook1-9/+33
Signed-off-by: Eric <eric.cook@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
2017-05-03drm/amd/display: Add function to set dither optionDing Wang9-58/+160
Signed-off-by: Ding Wang <Ding.Wang@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: Check for Zero Range in FreeSync CalcEric Cook1-0/+15
-check for min/max range in freesync calculation and handle it accordingly Signed-off-by: Eric <eric.cook@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
2017-05-03drm/amd/display: fix crash caused by incorrect index being used for arrayDmytro Laktyushkin1-1/+1
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
2017-05-03drm/amd/display: Define dithering optionsDing Wang2-1/+30
Signed-off-by: Ding Wang <Ding.Wang@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: decouple resource_pool from resource_contextTony Cheng13-147/+161
to avoid null access in case res_ctx is used to access res_pool before it's fully constructed also make it clear which function has dependency on resource_pool Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
2017-05-03drm/amd/display: FreeSync Auto Sweep SupportEric Cook13-123/+357
Implement core support to allow for FreeSync Auto Sweep to work Signed-off-by: Eric Cook <Eric.Cook@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: no need for return value from ipp_program_degamma_pwlDmytro Laktyushkin1-1/+1
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: dce80, 100, 110 and 112 to dce ipp refactorDmytro Laktyushkin15-848/+171
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: dce120 to dce ipp refactorDmytro Laktyushkin14-525/+521
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: clarify delay param for REG_WAITTony Cheng1-2/+2
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
2017-05-03drm/amd/display: move tg_color to dc_hw_typesTony Cheng2-18/+6
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
2017-05-03drm/amd/display: PSR RefactorSylvia Tsai11-150/+93
- Refacotr PSR to follow correct module pattern - fix eDP only working on sink index 0. Signed-off-by: Sylvia Tsai <sylvia.tsai@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: Make dc_link param const in set_drive_settingsZeyu Fan2-2/+2
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: improve cursor programming reliabilityDmytro Laktyushkin7-41/+32
This change will cache cursor attributes and reprogram them when enabling cursor after power gating if the attributes were not yet reprogrammed Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: USB-c DP-HDMI dongle shows garbage on Sony TVCharlene Liu4-4/+47
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
2017-05-03drm/amd/display: Make sure v_total_min and max not less than v_total.Yongqiang Sun3-4/+16
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: always retrieve PSR capAmy Zhang1-2/+1
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: fix memory leakDmytro Laktyushkin1-14/+12
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
2017-05-03drm/amd/display: set correct v_total_min and v_total_max for dce.Yongqiang Sun2-4/+4
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: remove unnecessary allocation for regamma_params inside oppDmytro Laktyushkin4-17/+5
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
2017-05-03drm/amd/display: Fix memory leak in post_update_surfacesHarry Wentland1-2/+5
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: Block YCbCr formats for eDP. Revert previous change.Zeyu Fan1-2/+6
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
2017-05-03drm/amd/display: get_atomic_property missing for drm_connector_funcsPratik Vishwakarma2-1/+58
DRM_IOCTL_MODE_GETCONNECTOR fails with EINVAL on enabling DRIVER_ATOMIC With this DRM_IOCTL_MODE_GETCONNECTOR returns all the connector properties. freesync_property and freesync_capable_property return 0 currently. TESTS(On Chromium OS on Stoney Only) * Builds without compilation errors. * 'atomictest' proceeds after applying patch and fails with vblank event timed out. * Chromium OS ui comes up. Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
2017-05-02drm/amdgpu/gfx9: wait for completion in KIQ initAlex Deucher1-10/+79
We need to make sure the various init sequences submitted to KIQ complete before testing the rings. Reviewed-by: monk liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-02drm/amdgpu/gfx9: use new KIQ packet definesAlex Deucher1-11/+12
Rather than magic numbers. Reviewed-by: monk liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-02drm/amdgpu: add KIQ packet defines to soc15d.hAlex Deucher1-0/+82
Will be used in subsequent commits rather rather than magic numbers. Reviewed-by: monk liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-02drm/amdgpu/gfx9: clear the compute ring on resetAlex Deucher1-0/+1
To be consistent with gfx8. Reviewed-by: monk liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-02drm/amdgpu/gfx9: create mqd backupsAlex Deucher1-2/+14
And properly synchronize them with the master during queue init. Reviewed-by: monk liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-02drm/amdgpu/gfx9: add additional MQD initializationAlex Deucher1-0/+5
Need to properly set the ROQ space setting. Reviewed-by: monk liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-02drm/amdgpu/gfx9: fix typo in mpd initAlex Deucher1-2/+2
Using the wrong macro for soc15 register access. Reviewed-by: monk liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-02drm/amdgpu/gfx9: use actual gpu num se setting for ngg allocationAlex Deucher1-2/+1
Rather than using a hardcoded value. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-02drm/amdgpu: update revision id settings for BR/STAlex Deucher1-0/+12
Add new RIDs. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Xie <AlexBin.Xie@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-01drm/amdgpu: Reserve 0-2 invalidation reg sets for none-amdgpu usagesShaoyun Liu1-1/+1
Firmware used reg set 2 for tlb invalidation. AMDGPU can start from reg set 3 to avoid the conflict. AMDKFD will use the reg set 0 or 1 when necesary. Change-Id: I71c595701f47110df0242d6926607c94bd5644eb Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewws-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-01drm/amdgpu: Move kiq ring lock out of virt structureShaoyun Liu5-6/+9
The usage of kiq should not depend on the virtualization. Change-Id: I39a439383b0c48d8f410cd362325b8404382cd53 Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by:Andres Rodriquez <andresx7@gmail.com>
2017-04-28drm/amdgpu: Make amdgpu_bo_reserve use uninterruptible waits for cleanupMichel Dänzer16-36/+36
Some of these paths probably cannot be interrupted by a signal anyway. Those that can would fail to clean up things if they actually got interrupted. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2017-04-28Revert "drm/amdgpu: Refactor flip into prepare submit and submit. (v2)"Michel Dänzer2-135/+29
This reverts commit cb341a319f7e66f879d69af929c3dadfc1a8f31e. The purpose of the refactor was for amdgpu_crtc_prepare/submit_flip to be used by the DC code, but that's no longer the case. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2017-04-28drm/amd/powerplay: implement stop dpm task for vega10.Rex Zhu5-1/+123
Change-Id: I50cc40001bd4d6cd033af70568a54909bf0a0601 Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com>
2017-04-28drm/amd/powerplay: complete disable_smc_firmware_ctf_tasks.Rex Zhu3-1/+7
Change-Id: I0e332e8f5608a6ffdc4dc67c2ac88b67f307fab8 Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com>
2017-04-28drm/amd/powerplay: add disable_smc_ctf callback in hwmgr.Rex Zhu4-1/+13
export disablesmcctf to eventmgr. need to disable temperature alert when s3/s4. otherwise, when resume back,enable temperature alert will fail. Change-Id: Id866969f70eb774690ec435013a076f1957de4ea Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com>
2017-04-28drm/amdgpu: add cu info wave_front_sizeJunwei Zhang1-0/+1
Change-Id: Icd2781355b147f3062e6bc4893745dc1b084dee1 Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
2017-04-28drm/amdgpu: fix deadlock of reservation between cs and gpu reset v2Chunming Zhou1-0/+4
the case could happen when gpu reset: 1. when gpu reset, cs can be continue until sw queue is full, then push job will wait with holding pd reservation. 2. gpu_reset routine will also need pd reservation to restore page table from their shadow. 3. cs is waiting for gpu_reset complete, but gpu reset is waiting for cs releases reservation. v2: handle amdgpu_cs_submit error path. Change-Id: I0f66d04b2bef3433035109623c8a5c5992c84202 Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com>
2017-04-28drm/amdgpu: bump module verion for reserved vmidChunming Zhou1-1/+2
Change-Id: I1065e0430ed44f7ee6c29214b72e35a7343ea02b Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2017-04-28drm/amdgpu: implement grab reserved vmid V4Chunming Zhou1-4/+75
v2: move sync waiting only when flush needs v3: fix racy v4: peek fence instead of get fence, and fix potential context starved. Change-Id: I64da2701c9fdcf986afb90ba1492a78d5bef1b6c Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2017-04-28drm/amdgpu: add limitation for dedicated vm number v4Chunming Zhou2-0/+12
v2: move #define to amdgpu_vm.h v3: move reserved vmid counter to id_manager, and increase counter before allocating vmid v4: rename to reserved_vmid_num Change-Id: Ie5958cf6dbdc1c8278e61d9158483472d6f5c6e3 Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2017-04-28drm/amdgpu: reserve/unreserve vmid by vm ioctl v4Chunming Zhou1-13/+49
add reserve/unreserve vmid funtions. v3: only reserve vmid from gfxhub v4: fix racy condition Change-Id: I5f80dc39dc9d44660a96a2b710b0dbb4d3b9039d Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 03:25:15 +0000